Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology. - Douglas C. Bossen; Alongkorn Kitamorn; Kevin Reick; Michael S. Floyd (IBM J. Res. Dev., 2002)

Power4 System Design for High Reliability. - Douglas C. Bossen; Joel M. Tendler; Kevin Reick (IEEE Micro, 2002)

Fault-Tolerant Design of the IBM Power6 Microprocessor. - Kevin Reick; Pia N. Sanda; Scott B. Swaney; Jeffrey W. Kellington; Michael J. Mack; Michael S. Floyd; Daniel Henderson (IEEE Micro, 2008)

Post-Silicon Validation of the IBM POWER8 Processor. - Amir Nahir; Manoj Dusanapudi; Shakti Kapoor; Kevin Reick; Wolfgang Roesner; Klaus-Dieter Schubert; Keith Sharp; Greg Wetli (DAC, 2014)

Debugging post-silicon fails in the IBM POWER8 bring-up lab. - Manoj Dusanapudi; S. Fields; Michael S. Floyd; Guy L. Guthrie; Ronald N. Kalla; Shakti Kapoor; Larry S. Leitner; Charles F. Marino; Joseph McGill; Amir Nahir; Kevin Reick; H. Shen; et al. (IBM J. Res. Dev., 2015)

Post-Silicon Validation of the IBM POWER9 Processor. - Tom Kolan; Hillel Mendelson; Vitali Sokhin; Kevin Reick; Elena Tsanko; Greg Wetli (DATE, 2020)