Design and applications of a scanning SQUID microscope. - John R. Kirtley; Mark B. Ketchen; Chang C. Tsuei; Jonathan Z. Sun; William J. Gallagher; Lock See Yu-Jahnes; Arunava Gupta; Kevin G. Stawiasz; Shalom J. Wind (IBM J. Res. Dev., 1995)

High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. - David F. Heidel; Sang H. Dhong; H. Peter Hofstee; Michael Immediato; Kevin J. Nowka; Joel Silberman; Kevin Stawiasz (VTS, 1998)

Designing a Testable System on a Chip. - Stephen V. Kosonocky; Arthur A. Bright; Kevin W. Warren; Ruud A. Haring; Steve Klepner; Sameh W. Asaad; S. Basavaiah; Bob Havreluk; David F. Heidel; Michael Immediato; Keith A. Jenkins; Rajiv V. Joshi; et al. (VTS, 1998)

A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology. - Jungwook Yang; Joongho Choi; Daniel M. Kuchta; Kevin G. Stawiasz; Petar K. Pepeljugoski; Herschel A. Ainspan (IEEE J. Solid State Circuits, 1998)

Minimizing inductive noise in system-on-a-chip with multiple power gating structures. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel; Kevin Stawiasz; David F. Heidel; Michael Immediato (ESSCIRC, 2003)

Experimental measurement of a novel power gating structure with intermediate power saving mode. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel; Kevin Stawiasz (ISLPED, 2004)

A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel; Kevin Stawiasz; Marios C. Papaefthymiou (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. - Azeez J. Bhavnagarwala; Stephen Kosonocky; Carl Radens; Yuen H. Chan; Kevin Stawiasz; Uma Srinivasan 002; Steven P. Kowalczyk; Matthew M. Ziegler (IEEE J. Solid State Circuits, 2008)

A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS. - Masood Qazi; Kevin Stawiasz; Leland Chang; Anantha P. Chandrakasan (ISSCC, 2010)

A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS. - Masood Qazi; Kevin Stawiasz; Leland Chang; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2011)

Performance impact of through-silicon vias (TSVs) in three-dimensional technology measured by SRAM ring oscillators. - Jente B. Kuang; Keith A. Jenkins; Kevin Stawiasz; Jeremy D. Schaub (ESSCIRC, 2013)

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. - Zeynep Toprak Deniz; Michael A. Sperling; John F. Bulzacchelli; Gregory S. Still; Ryan Kruse; Seongwon Kim; David Boerstler; Tilman Gloekler; Raphael Robertazzi; Kevin Stawiasz; Tim Diemoz; George English; et al. (ISSCC, 2014)

5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. - Eric J. Fluhr; Joshua Friedrich; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; Allen Hall; David Hogenmiller; Frank Malgioglio; Ryan Nett; Jose Paredes; Juergen Pille; et al. (ISSCC, 2014)

SOI FinFET soft error upset susceptibility and analysis. - Phil Oldiges; Kenneth P. Rodbell; Michael S. Gordon; John G. Massey; Kevin Stawiasz; Conal E. Murray; Henry H. K. Tang; K. Kim; K. Paul Muller (IRPS, 2015)

Analyzing path delays for accelerated testing of logic chips. - Emily Ray; Barry P. Linder; Raphael Robertazzi; Kevin Stawiasz; Alan J. Weger; Emmanuel Yashchin; James H. Stathis; Peilin Song (IRPS, 2015)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)