Shepard: A fast exact match short read aligner. - Chad Nelson; Kevin Townsend; Bhavani Satyanarayana Rao; Phillip H. Jones; Joseph Zambreno (MEMOCODE, 2012)

Reduce, Reuse, Recycle (R3): A design methodology for Sparse Matrix Vector Multiplication on reconfigurable platforms. - Kevin Townsend; Joseph Zambreno (ASAP, 2013)

A 15-bit binary-weighted current-steering DAC with ordered element matching. - Tao Zeng; Kevin Townsend; Jingbo Duan; Degang Chen 001 (CICC, 2013)

CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search. - Osama G. Attia; Tyler Johnson; Kevin Townsend; Phillip H. Jones; Joseph Zambreno (IPDPS Workshops, 2014)

A high performance systolic architecture for k-NN classification. - Kevin Townsend; Phillip H. Jones; Joseph Zambreno (MEMOCODE, 2014)

k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator. - Kevin R. Townsend; Song Sun; Tyler Johnson; Osama G. Attia; Phillip H. Jones; Joseph Zambreno (EIT, 2015)

A multi-phase approach to floating-point compression. - Kevin R. Townsend; Joseph Zambreno (EIT, 2015)

Accelerating all-pairs shortest path using a message-passing reconfigurable architecture. - Osama G. Attia; Alex Grieve; Kevin R. Townsend; Phillip H. Jones; Joseph Zambreno (ReConFig, 2015)

A Scalable Unsegmented Multiport Memory for FPGA-Based Systems. - Kevin R. Townsend; Osama G. Attia; Phillip H. Jones; Joseph Zambreno (Int. J. Reconfigurable Comput., 2015)

RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing. - Chad Nelson; Kevin R. Townsend; Osama G. Attia; Phillip H. Jones; Joseph Zambreno (IEEE Trans. Parallel Distributed Syst., 2016)

A Reconfigurable Architecture for the Detection of Strongly Connected Components. - Osama G. Attia; Kevin R. Townsend; Phillip H. Jones; Joseph Zambreno (ACM Trans. Reconfigurable Technol. Syst., 2016)