Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. - Fatih Hamzaoglu; Yibin Ye; Ali Keshavarzi; Kevin Zhang 001; Siva G. Narendra; Shekhar Borkar; Mircea R. Stan; Vivek De (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. - Ali Keshavarzi; Gerhard Schrom; Stephen Tang; Sean Ma; Keith A. Bowman; Sunit Tyagi; Kevin Zhang 001; Tom Linton; Nagib Hakim; Steven G. Duvall; John Brews; Vivek De (ISLPED, 2005)

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. - Kevin Zhang 001; Uddalak Bhattacharya; Zhanping Chen; Fatih Hamzaoglu; Daniel Murray; Narendra Vallepalli; Yih Wang; Bo Zheng; Mark Bohr (IEEE J. Solid State Circuits, 2005)

A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. - Muhammad M. Khellah; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Yibin Ye; James W. Tschanz; Dinesh Somasekhar; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; Kevin Zhang 001; et al. (ISSCC, 2006)

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. - Kevin Zhang 001; Uddalak Bhattacharya; Zhanping Chen; Fatih Hamzaoglu; Daniel Murray; Narendra Vallepalli; Yih Wang; Bo Zheng; Mark Bohr (IEEE J. Solid State Circuits, 2006)

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; Ian Post; et al. (ISSCC, 2007)

SRAM. - Kevin Zhang 001; Hiroyuki Yamauchi (ISSCC, 2007)

A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. - Muhammad M. Khellah; Dinesh Somasekhar; Yibin Ye; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Murad Sunna; James W. Tschanz; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; et al. (IEEE J. Solid State Circuits, 2007)

A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology. - Fatih Hamzaoglu; Kevin Zhang 001; Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Yong-Gee Ng; Andrei Pavlov; Ken Smits; Mark Bohr (ISSCC, 2008)

Embedded Memory Design for Nano-Scale VLSI Systems (Forum). - Kevin Zhang 001 (ISSCC, 2008)

A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; et al. (IEEE J. Solid State Circuits, 2008)

Circuit design in nano-scale CMOS era: opportunities & challenges. - Kevin Zhang 001 (ISLPED, 2009)

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management. - Yih Wang; Uddalak Bhattacharya; Fatih Hamzaoglu; Pramod Kolar; Yong-Gee Ng; Liqiong Wei; Ying Zhang; Kevin Zhang 001; Mark Bohr (ISSCC, 2009)

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology. - Fatih Hamzaoglu; Kevin Zhang 001; Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Yong-Gee Ng; Andrei Pavlov; Ken Smits; Mark Bohr (IEEE J. Solid State Circuits, 2009)

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. - Muhammad M. Khellah; Nam-Sung Kim; Yibin Ye; Dinesh Somasekhar; Tanay Karnik; Nitin Borkar; Gunjan Pandya; Fatih Hamzaoglu; Tom Coan; Yih Wang; Kevin Zhang 001; Clair Webb; et al. (IEEE J. Solid State Circuits, 2009)

A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation. - Hyunwoo Nho; Pramod Kolar; Fatih Hamzaoglu; Yih Wang; Eric Karl; Yong-Gee Ng; Uddalak Bhattacharya; Kevin Zhang 001 (ISSCC, 2010)

A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS. - Sarvesh H. Kulkarni; Zhanping Chen; Jun He; Lei Jiang 013; Brian Pedersen; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2010)

Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. - Dinesh Somasekhar; Balaji Srinivasan; Gunjan Pandya; Fatih Hamzaoglu; Muhammad M. Khellah; Tanay Karnik; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2010)

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. - Yih Wang; Uddalak Bhattacharya; Fatih Hamzaoglu; Pramod Kolar; Yong-Gee Ng; Liqiong Wei; Ying Zhang; Kevin Zhang 001; Mark Bohr (IEEE J. Solid State Circuits, 2010)

Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design. - Fatih Hamzaoglu; Yih Wang; Pramod Kolar; Liqiong Wei; Yong-Gee Ng; Uddalak Bhattacharya; Kevin Zhang 001 (IEEE Des. Test Comput., 2011)

A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation. - Pramod Kolar; Eric Karl; Uddalak Bhattacharya; Fatih Hamzaoglu; Henry Nho; Yong-Gee Ng; Yih Wang; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2011)

Challenges and opportunities for circuit design in nano-scale CMOS technologies. - Kevin Zhang 001 (ESSCIRC, 2012)

A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. - Eric Karl; Yih Wang; Yong-Gee Ng; Zheng Guo; Fatih Hamzaoglu; Uddalak Bhattacharya; Kevin Zhang 001; Kaizad Mistry; Mark Bohr (ISSCC, 2012)

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. - Eric Karl; Yih Wang; Yong-Gee Ng; Zheng Guo; Fatih Hamzaoglu; Mesut Meterelliyoz; John Keane 001; Uddalak Bhattacharya; Kevin Zhang 001; Kaizad Mistry; Mark Bohr (IEEE J. Solid State Circuits, 2013)

13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. - Fatih Hamzaoglu; Umut Arslan; Nabhendra Bisnik; Swaroop Ghosh; Manoj B. Lal; Nick Lindert; Mesut Meterelliyoz; Randy B. Osborne; Joodong Park; Shigeki Tomishima; Yih Wang; Kevin Zhang 001 (ISSCC, 2014)

2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology. - Mesut Meterelliyoz; Fuad H. Al-amoody; Umut Arslan; Fatih Hamzaoglu; Luke Hood; Manoj B. Lal; Jeffrey L. Miller; Anand Ramasundar; Dan Soltman; Ifar Wan; Yih Wang; Kevin Zhang 001 (VLSIC, 2014)

17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology. - Eric Karl; Zheng Guo; James W. Conary; Jeffrey L. Miller; Yong-Gee Ng; Satyanand Nalam; Daeyeon Kim; John Keane 001; Uddalak Bhattacharya; Kevin Zhang 001 (ISSCC, 2015)

A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist. - Kyung-Hoae Koo; Liqiong Wei; John Keane 001; Uddalak Bhattacharya; Eric A. Karl; Kevin Zhang 001 (VLSIC, 2015)

Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process. - Sarvesh H. Kulkarni; Zhanping Chen; Balaji Srinivasan; Brian Pedersen; Uddalak Bhattacharya; Kevin Zhang 001 (VLSIC, 2015)

A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology. - Fatih Hamzaoglu; Umut Arslan; Nabhendra Bisnik; Swaroop Ghosh; Manoj B. Lal; Nick Lindert; Mesut Meterelliyoz; Randy B. Osborne; Joodong Park; Shigeki Tomishima; Yih Wang; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2015)

Session 1 overview: Plenary session. - Anantha P. Chandrakasan; Kevin Zhang 001 (ISSCC, 2016)

17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology. - John Keane 001; Jaydeep Kulkarni; Kyung-Hoae Koo; Satyanand Nalam; Zheng Guo; Eric Karl; Kevin Zhang 001 (ISSCC, 2016)

Foreword: Silicon systems for the Internet of Everything. - Kevin Zhang 001 (ISSCC, 2016)

A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating. - Zhanping Chen; Sarvesh H. Kulkarni; Vincent E. Dorgan; Uddalak Bhattacharya; Kevin Zhang 001 (VLSI Circuits, 2016)

A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry. - Eric Karl; Zheng Guo; James W. Conary; Jeffrey L. Miller; Yong-Gee Ng; Satyanand Nalam; Daeyeon Kim; John Keane 001; Xiaofei Wang; Uddalak Bhattacharya; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2016)

A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS. - Sarvesh H. Kulkarni; Zhanping Chen; Balaji Srinivasan; Brian Pedersen; Uddalak Bhattacharya; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2016)

5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology. - Jaydeep P. Kulkarni; John Keane 001; Kyung-Hoae Koo; Satyanand Nalam; Zheng Guo; Eric Karl; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2017)

Circuit Design in Nano-Scale CMOS Technologies. - Kevin Zhang 001 (A-SSCC, 2018)

Session 1 Overview Plenary Session - Invited Papers. - Kevin Zhang 001; Makoto Ikeda (ISSCC, 2021)

1.1 Semiconductor Industry: Present & Future. - Kevin Zhang 001 (ISSCC, 2024)