Multiple Faults in Reed-Muller Canonic Networks - Kewal K. Saluja; Sudhakar M. Reddy (SWAT, 1972)

On Minimally Testable Logic Networks. - Kewal K. Saluja; Sudhakar M. Reddy (IEEE Trans. Computers, 1974)

Easily Testable Two-Dimensional Cellular Logic Arrays. - Kewal K. Saluja; Sudhakar M. Reddy (IEEE Trans. Computers, 1974)

Fault Detecting Test Sets for Reed-Muller Canonic Networks. - Kewal K. Saluja; Sudhakar M. Reddy (IEEE Trans. Computers, 1975)

Minimization of Reed-Muller Canonic Expansion. - Kewal K. Saluja; E. H. Ong (IEEE Trans. Computers, 1979)

Fault diagnosis in loop-connected systems. - Kewal K. Saluja; Brian D. O. Anderson (Inf. Sci., 1980)

Synchronous Sequential Machines: A Modular and Testable Design. - Kewal K. Saluja (IEEE Trans. Computers, 1980)

An enhancement of lssd to reduce test pattern generation effort and increase fault coverage. - Kewal K. Saluja (DAC, 1982)

Testing Computer Hardware through Data Compression in Space and Time. - Kewal K. Saluja; Mark G. Karpovsky (ITC, 1983)

A Simplified Algorithm for Testing Microprocessors. - Kewal K. Saluja; Li Shen; Stephen Y. H. Su (ITC, 1983)

An Easily Testable Design of Programmable Logic Arrays for Multiple Faults. - Kewal K. Saluja; Kozo Kinoshita; Hideo Fujiwara (IEEE Trans. Computers, 1983)

Built-in Testing of Memory Using On-chip Compact Testing Scheme. - Kozo Kinoshita; Kewal K. Saluja (ITC, 1984)

Testable design of large random access memories. - Kewal K. Saluja; Kim Thang Le (Integr., 1984)

A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. - Hideo Fujiwara; Kewal K. Saluja; Kozo Kinoshita (ITC, 1985)

Design of Programmable Logic Arrays for Parallel Testing. - C. Boswell; Kewal K. Saluja; Kozo Kinoshita (Comput. Syst. Sci. Eng., 1985)

Test Pattern Generation for API Faults in RAM. - Kewal K. Saluja; Kozo Kinoshita (IEEE Trans. Computers, 1985)

A Novel Approach for Testing Memories Using a Built-In Self Testing Technique. - Kim T. Le; Kewal K. Saluja (ITC, 1986)

Built-In Testing of Memory Using an On-Chip Compact Testing Scheme. - Kozo Kinoshita; Kewal K. Saluja (IEEE Trans. Computers, 1986)

An Alternative to Scan Design Methods for Sequential Machines. - Kewal K. Saluja; Ramaswami Dandapani (IEEE Trans. Computers, 1986)

Testable Design of Single-Output Sequential Machines Using Checking Experiments. - Kewal K. Saluja; Ramaswami Dandapani (IEEE Trans. Computers, 1986)

A Wachtdog Processor Based General Rollback Technique with Multiple Retries. - Shambhu J. Upadhyaya; Kewal K. Saluja (IEEE Trans. Software Eng., 1986)

BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays. - Chun-Yeh Liu; Kewal K. Saluja; Shambhu J. Upadhyaya (DAC, 1987)

Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. - Kifung C. Cheung; Gurindar S. Sohi; Kewal K. Saluja; Dhiraj K. Pradhan (ISCA, 1987)

Built-In Self-Testing RAM: A Practical Alternative. - Kewal K. Saluja; Siew H. Sng; Kozo Kinoshita (IEEE Des. Test, 1987)

An implementation and analysis of a concurrent built-in self-test technique. - Rajiv Sharma; Kewal K. Saluja (FTCS, 1988)

Test Scheduling and Control for VLSI Built-In Self-Test. - Gary L. Craig; Charles R. Kime; Kewal K. Saluja (IEEE Trans. Computers, 1988)

A Data Compression Technique for Built-In Self-Test. - Sudhakar M. Reddy; Kewal K. Saluja; Mark G. Karpovsky (IEEE Trans. Computers, 1988)

An experimental study to determine task size for rollback recovery systems. - Shambhu J. Upadhyaya; Kewal K. Saluja (IEEE Trans. Computers, 1988)

A concurrent testing technique for digital circuits. - Kewal K. Saluja; Rajiv Sharma; Charles R. Kime (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

A new approach to the design of built-in self-testing PLAs for high fault coverage. - Shambhu J. Upadhyaya; Kewal K. Saluja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Row/column pattern sensitive fault detection in RAMs via built-in self-test. - Manoj Franklin; Kewal K. Saluja; Kozo Kinoshita (FTCS, 1989)

A study of time-redundant fault tolerance techniques for high-performance pipelined computers. - Gurindar S. Sohi; Manoj Franklin; Kewal K. Saluja (FTCS, 1989)

Fast test generation for sequential circuits. - Todd P. Kelsey; Kewal K. Saluja (ICCAD, 1989)

Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability. - Manoj Franklin; Kewal K. Saluja; Kozo Kinoshita (ITC, 1989)

Built-in Self-testing of Random-Access Memories. - Manoj Franklin; Kewal K. Saluja (Computer, 1990)

Improved Test Generation for High-Activity Circuits. - Kewal K. Saluja; Kyuchull Kim (IEEE Des. Test Comput., 1990)

Design and Analysis of a Gracefully Degrading Interleaved Memory System. - Kifung C. Cheung; Gurindar S. Sohi; Kewal K. Saluja; Dhiraj K. Pradhan (IEEE Trans. Computers, 1990)

A built-in self-test algorithm for row/column pattern sensitive faults in RAMs. - Manoj Franklin; Kewal K. Saluja; Kozo Kinoshita (IEEE J. Solid State Circuits, 1990)

Pattern Sensitive Fault Testing of RAMs with Bullt-in ECC. - Manoj Franklin; Kewal K. Saluja (FTCS, 1991)

An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults. - Manoj Franklin; Kewal K. Saluja (ITC, 1991)

A method of reducing aliasing in a built-in self-test environment. - Keiho Akiyama; Kewal K. Saluja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Incorporating Testability Considerations in High-Level Systhesis. - Ashutosh Mujumdar; Kewal K. Saluja; Rajiv Jain (FTCS, 1992)

An algorithm to reduce test application time in full scan designs. - Soo Young Lee; Kewal K. Saluja (ICCAD, 1992)

An Efficient Method for Computation of Signatures. - Chin-Foo See; Kewal K. Saluja (VLSI Design, 1992)

On fault deletion problem in concurrent fault simulation for synchronous sequential circuits. - Kyuchull Kim; Kewal K. Saluja (VTS, 1992)

Zero cost testing of check bits in RAMs with on-chip ECC. - Parameswaran Ramanathan; Kewal K. Saluja; Michael J. Franklin (VTS, 1992)

An Efficient Signature Computation Method. - Kewal K. Saluja; Chin-Foo See (IEEE Des. Test Comput., 1992)

Efficient Test Vectors for ISCAS Sequential Benchmark Circuits. - Soo Young Lee; Kewal K. Saluja (ISCAS, 1993)

CCSTG: an efficient test pattern generator for sequential circuits. - Kyuchull Kim; Kewal K. Saluja (VTS, 1993)

A Tutorial on Built-in Self-Test. I. Principles. - Vishwani D. Agrawal; Charles R. Kime; Kewal K. Saluja (IEEE Des. Test Comput., 1993)

A Tutorial on Built-In Self-Test, Part 2: Applications. - Vishwani D. Agrawal; Charles R. Kime; Kewal K. Saluja (IEEE Des. Test Comput., 1993)

An Efficient Algorithm for Sequential Circuit Test Generation. - Todd P. Kelsey; Kewal K. Saluja; Soo Young Lee (IEEE Trans. Computers, 1993)

An efficient algorithm for bipartite PLA folding. - Chun-Yeh Liu; Kewal K. Saluja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Theory, Analysis and Implementation of an On-Line BIST Technique. - Rajiv Sharma; Kewal K. Saluja (VLSI Design, 1993)

Behavioral Synthesis of Testable Designs. - Ashutosh Mujumdar; Rajiv Jain; Kewal K. Saluja (FTCS, 1994)

Power Constraint Scheduling of Tests. - Richard M. Chou; Kewal K. Saluja; Vishwani D. Agrawal (VLSI Design, 1994)

An Algorithm to Test Reconfigured RAMs. - Manoj Franklin; Kewal K. Saluja (VLSI Design, 1994)

Sequential test generation with reduced test clocks for partial scan designs. - Soo Young Lee; Kewal K. Saluja (VTS, 1994)

Incorporating testability considerations in high-level synthesis. - Ashutosh Mujumdar; Rajiv Jain; Kewal K. Saluja (J. Electron. Test., 1994)

On-chip testing of random access memories. - Kewal K. Saluja (J. Electron. Test., 1994)

Hypergraph Coloring and Reconfigured RAM Testing. - Manoj Franklin; Kewal K. Saluja (IEEE Trans. Computers, 1994)

Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan. - Ning Jiang; Richard M. Chou; Kewal K. Saluja (FTCS, 1995)

Test application time reduction for scan based sequential circuits. - Hao Zheng; Kewal K. Saluja; Rajiv Jain (Great Lakes Symposium on VLSI, 1995)

Fast computation of MISR signatures. - Manoj Franklin; Kewal K. Saluja; Kyuchull Kim (VLSI Design, 1995)

An optimized testable architecture for finite state machines. - Ting-Yu Kuo; Chun-Yeh Liu; Kewal K. Saluja (VTS, 1995)

Test application time reduction for sequential circuits with scan. - Soo Young Lee; Kewal K. Saluja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Random Pattern Testing for Sequential Circuits Revisited. - Lama Nachman; Kewal K. Saluja; Shambhu J. Upadhyaya; Robert Reuse (FTCS, 1996)

A new method towards achieving global optimality in technology mapping. - Xiaoqing Wen; Kewal K. Saluja (ICCAD, 1996)

Methods for Dynamic Test Vector compaction in Sequential Test Generation. - Timothy John Lambert; Kewal K. Saluja (VLSI Design, 1996)

Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults. - Manoj Franklin; Kewal K. Saluja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Incorporating performance and testability constraints during binding in high-level synthesis. - Ashutosh Mujumdar; Rajiv Jain; Kewal K. Saluja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits. - Kyuchull Kim; Kewal K. Saluja (VLSI Design, 1996)

Sequential Circuit Testing: From DFT to SFT. - Richard M. Chou; Kewal K. Saluja (VLSI Design, 1997)

Guest Editorial. - Kwang-Ting Cheng; Kewal K. Saluja; Hans-Joachim Wunderlich (J. Electron. Test., 1997)

Scheduling tests for VLSI systems under power constraints. - Richard M. Chou; Kewal K. Saluja; Vishwani D. Agrawal (IEEE Trans. Very Large Scale Integr. Syst., 1997)

Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. - Yoshinobu Higami; Kewal K. Saluja; Kozo Kinoshita (Asian Test Symposium, 1998)

Design for Diagnosability of CMOS Circuits. - Xiaoqing Wen; Tooru Honzawa; Hideo Tamamoto; Kewal K. Saluja; Kozo Kinoshita (Asian Test Symposium, 1998)

On Test Pattern Compaction Using Random Pattern Fault Simulation. - Seiji Kajihara; Kewal K. Saluja (VLSI Design, 1998)

A Heuristic Measure to Maximize Detected Faults per Test. - Kim T. Le; Kewal K. Saluja (J. Electron. Test., 1998)

Sequential test generators: past, present and future. - Yong Chang Kim; Kewal K. Saluja (Integr., 1998)

A Novel Approach to Random Pattern Testing of Sequential Circuits. - Lama Nachman; Kewal K. Saluja; Shambhu J. Upadhyaya; Robert Reuse (IEEE Trans. Computers, 1998)

Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. - Yoshinobu Higami; Yuzo Takamatsu; Kewal K. Saluja; Kozo Kinoshita (Asian Test Symposium, 1999)

A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability. - Yong Chang Kim; Kewal K. Saluja; Vishwani D. Agrawal (Great Lakes Symposium on VLSI, 1999)

Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. - Yoshinobu Higami; Kewal K. Saluja; Kozo Kinoshita (VLSI Design, 1999)

Fault models and test generation for IDDQ testing: embedded tutorial. - Yoshinobu Higami; Yuzo Takamatsu; Kewal K. Saluja; Kozo Kinoshita (ASP-DAC, 2000)

Fault Tolerance through Re-Execution in Multiscalar Architecture. - Faisal Rashid; Kewal K. Saluja; Parameswaran Ramanathan (DSN, 2000)

Testing Flash Memories. - Mohammad Gh. Mohammad; Kewal K. Saluja; Alex S. Yap (VLSI Design, 2000)

Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. - Hiroki Wada; Toshimitsu Masuzawa; Kewal K. Saluja; Hideo Fujiwara (VLSI Design, 2000)

Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. - Yoshinobu Higami; Yuzo Takamatsu; Kewal K. Saluja; Kozo Kinoshita (J. Electron. Test., 2000)

Static test compaction for IDDQ testing of bridging faults in sequential circuits. - Yoshinobu Higami; Kewal K. Saluja; Yuzo Takamatsu; Kozo Kinoshita (Syst. Comput. Jpn., 2000)

Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. - Hiroshi Takahashi; Marong Phadoongsidhi; Yoshinobu Higami; Kewal K. Saluja; Yuzo Takamatsu (Asian Test Symposium, 2001)

On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits. - Keith J. Keller; Hiroshi Takahashi; Kewal K. Saluja; Yuzo Takamatsu (ITC, 2001)

Combinational test generation for various classes of acyclic sequential circuits. - Yong Chang Kim; Vishwani D. Agrawal; Kewal K. Saluja (ITC, 2001)

Efficient Signature-Based Fault Diagnosis Using Variable Size Windows. - Thomas Clouqueur; Ozen Ercevik; Kewal K. Saluja; Hiroshi Takahashi (VLSI Design, 2001)

Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. - Yong Chang Kim; Kewal K. Saluja; Vishwani D. Agrawal (VLSI Design, 2001)

Testable Sequential Circuit Design: A Partition and Resynthesis Approach. - Richard M. Chou; Kewal K. Saluja (VTS, 2001)

Flash Memory Disturbances: Modeling and Test. - Mohammad Gh. Mohammad; Kewal K. Saluja (VTS, 2001)

Fault Models and Test Procedures for Flash Memory Disturbances. - Mohammad Gh. Mohammad; Kewal K. Saluja; Alex S. Yap (J. Electron. Test., 2001)

Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. - Keith J. Keller; Hiroshi Takahashi; Kim T. Le; Kewal K. Saluja; Yuzo Takamatsu (Asian Test Symposium, 2002)

A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits. - Marong Phadoongsidhi; Kim T. Le; Kewal K. Saluja (Asian Test Symposium, 2002)

Sensor deployment strategy for target detection. - Thomas Clouqueur; Veradej Phipatanasuphorn; Parameswaran Ramanathan; Kewal K. Saluja (WSNA, 2002)

An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets. - Hiroshi Takahashi; Kewal K. Saluja; Yuzo Takamatsu (PRDC, 2002)

Multiple Faults: Modeling, Simulation and Test. - Yong Chang Kim; Vishwani D. Agrawal; Kewal K. Saluja (ASP-DAC/VLSI Design, 2002)

Estimation of Maximum Power-Up Current. - Fei Li 003; Lei He 001; Kewal K. Saluja (ASP-DAC/VLSI Design, 2002)

Minimizing Energy Consumption for High-Performance Processing. - Eric F. Weglarz; Kewal K. Saluja; Mikko H. Lipasti (ASP-DAC/VLSI Design, 2002)

On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits. - Hiroshi Takahashi; Kwame Osei Boateng; Kewal K. Saluja; Yuzo Takamatsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Stress Test for Disturb Faults in Non-Volatile Memories. - Mohammad Gh. Mohammad; Kewal K. Saluja (Asian Test Symposium, 2003)

Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits. - Kewal K. Saluja (Asian Test Symposium, 2003)

Software-Based Delay Fault Testing of Processor Cores. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (Asian Test Symposium, 2003)

Fault Diagnosis for Physical Defects of Unknown Behaviors. - Xiaoqing Wen; Hideo Tamamoto; Kewal K. Saluja; Kozo Kinoshita (Asian Test Symposium, 2003)

Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits. - Marong Phadoongsidhi; Kewal K. Saluja (ICCD, 2003)

Exclusive Test and its Applications to Fault Diagnosis. - Vishwani D. Agrawal; Dong Hyun Baik; Yong Chang Kim; Kewal K. Saluja (VLSI Design, 2003)

Electrical Model For Program Disturb Faults in Non-Volatile Memories. - Mohammad Gh. Mohammad; Kewal K. Saluja (VLSI Design, 2003)

Sensor Deployment Strategy for Detection of Targets Traversing a Region. - Thomas Clouqueur; Veradej Phipatanasuphorn; Parameswaran Ramanathan; Kewal K. Saluja (Mob. Networks Appl., 2003)

Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. - Seiji Kajihara; Kewal K. Saluja; Sudhakar M. Reddy (ETS, 2004)

A yield improvement methodology using pre- and post-silicon statistical clock scheduling. - Jeng-Liang Tsai; Dong Hyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja (ICCAD, 2004)

On per-test fault diagnosis using the X-fault model. - Xiaoqing Wen; Tokiharu Miyoshi; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja; Kozo Kinoshita (ICCAD, 2004)

Testing of Hard Faults in Simultaneous Multithreaded Processors. - Eric F. Weglarz; Kewal K. Saluja; T. M. Mak (IOLTS, 2004)

Testing Micropipelined Asynchronous Circuits. - Matthew L. King; Kewal K. Saluja (ITC, 2004)

Random Access Scan: A solution to test power, test data volume and test time. - Dong Hyun Baik; Kewal K. Saluja; Seiji Kajihara (VLSI Design, 2004)

Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults. - Marong Phadoongsidhi; Kewal K. Saluja (VLSI Design, 2004)

Instruction-Based Delay Fault Self-Testing of Processor Cores. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (VLSI Design, 2004)

Fault Tolerance in Collaborative Sensor Networks for Target Detection. - Thomas Clouqueur; Kewal K. Saluja; Parameswaran Ramanathan (IEEE Trans. Computers, 2004)

State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size. - Dong Hyun Baik; Kewal K. Saluja (Asian Test Symposium, 2005)

A Class of Linear Space Compactors for Enhanced Diagnostic. - Thomas Clouqueur; Hideo Fujiwara; Kewal K. Saluja (Asian Test Symposium, 2005)

Testing Superscalar Processors in Functional Mode. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (FPL, 2005)

Instruction-based delay fault self-testing of pipelined processor cores. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (ISCAS (6), 2005)

Progressive random access scan: a simultaneous solution to test power, test data volume and test time. - Dong Hyun Baik; Kewal K. Saluja (ITC, 2005)

Design and analysis of multiple weight linear compactors of responses containing unknown values. - Thomas Clouqueur; Kamran Zarrineh; Kewal K. Saluja; Hideo Fujiwara (ITC, 2005)

Low-capture-power test generation for scan-based at-speed testing. - Xiaoqing Wen; Yoshiyuki Yamashita; Shohei Morishima; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja; Kozo Kinoshita (ITC, 2005)

Exposure for collaborative detection using mobile sensor networks. - Tai-Lin Chin; Parameswaran Ramanathan; Kewal K. Saluja; Kuang-Ching Wang (MASS, 2005)

SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits. - Marong Phadoongsidhi; Kewal K. Saluja (VLSI Design, 2005)

False Path and Clock Scheduling Based Yield-Aware Gate Sizing. - Jeng-Liang Tsai; Dong Hyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja (VLSI Design, 2005)

On Low-Capture-Power Test Generation for Scan Testing. - Xiaoqing Wen; Yoshiyuki Yamashita; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja; Kozo Kinoshita (VTS, 2005)

Yield-Driven, False-Path-Aware Clock Skew Scheduling. - Jeng-Liang Tsai; Dong Hyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja (IEEE Des. Test Comput., 2005)

Delay Fault Testing of Processor Cores in Functional Mode. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2005)

On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies. - Xiaoqing Wen; Seiji Kajihara; Hideo Tamamoto; Kewal K. Saluja; Kozo Kinoshita (IEICE Trans. Inf. Syst., 2005)

Fault Diagnosis of Physical Defects Using Unknown Behavior Model. - Xiaoqing Wen; Hideo Tamamoto; Kewal K. Saluja; Kozo Kinoshita (J. Comput. Sci. Technol., 2005)

Efficient Test Set Modification for Capture Power Reduction. - Xiaoqing Wen; Tatsuya Suzuki; Seiji Kajihara; Kohei Miyase; Yoshihiro Minamoto; Laung-Terng Wang; Kewal K. Saluja (J. Low Power Electron., 2005)

Combinational automatic test pattern generation for acyclic sequential circuits. - Yong Chang Kim; Vishwani D. Agrawal; Kewal K. Saluja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Optimizing program disturb fault tests using defect-based testing. - Mohammad Gh. Mohammad; Kewal K. Saluja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits. - Hiroshi Takahashi; Keith J. Keller; Kim T. Le; Kewal K. Saluja; Yuzo Takamatsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (ASP-DAC, 2006)

Diagnosis of Transistor Shorts in Logic Test Environment. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Sin-ya Kobayashi; Yuzo Takamatsu (ATS, 2006)

Optimal Sensor Distribution for Maximum Exposure in A Region with Obstacles. - Tai-Lin Chin; Parameswaran Ramanathan; Kewal K. Saluja (GLOBECOM, 2006)

Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. - Xiaoqing Wen; Kohei Miyase; Tatsuya Suzuki; Yuta Yamato; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja (ICCD, 2006)

Analytic modeling of detection latency in mobile sensor networks. - Tai-Lin Chin; Parameswaran Ramanathan; Kewal K. Saluja (IPSN, 2006)

Test Cost Reduction Using Partitioned Grid Random Access Scan. - Dong Hyun Baik; Kewal K. Saluja (VLSI Design, 2006)

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. - Xiaoqing Wen; Seiji Kajihara; Kohei Miyase; Tatsuya Suzuki; Kewal K. Saluja; Laung-Terng Wang; Khader S. Abdel-Hafez; Kozo Kinoshita (VTS, 2006)

Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch. - Yoshiyuki Nakamura; Thomas Clouqueur; Kewal K. Saluja; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2006)

A Per-Test Fault Diagnosis Method Based on the X-Fault Model. - Xiaoqing Wen; Seiji Kajihara; Kohei Miyase; Yuta Yamato; Kewal K. Saluja; Laung-Terng Wang; Kozo Kinoshita (IEICE Trans. Inf. Syst., 2006)

A New Method for Low-Capture-Power Test Generation for Scan Testing. - Xiaoqing Wen; Yoshiyuki Yamashita; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja; Kozo Kinoshita (IEICE Trans. Inf. Syst., 2006)

Vulnerability of Surveillance Networks to Faults. - Tai-Lin Chin; Thomas Clouqueur; Parameswaran Ramanathan; Kewal K. Saluja (Int. J. Distributed Sens. Networks, 2006)

Energy Estimation of the Memory Subsystem in Multiprocessor Systems. - Eric F. Weglarz; Kewal K. Saluja; Mikko H. Lipasti (J. Low Power Electron., 2006)

Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (ATS, 2007)

Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. - Xiaoqing Wen; Kohei Miyase; Tatsuya Suzuki; Seiji Kajihara; Yuji Ohsumi; Kewal K. Saluja (DAC, 2007)

Combating NBTI Degradation via Gate Sizing. - Xiangning Yang; Kewal K. Saluja (ISQED, 2007)

Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Yuzo Takamatsu (VLSI Design, 2007)

Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. - Kim T. Le; Dong Hyun Baik; Kewal K. Saluja (VLSI Design, 2007)

On NBTI Degradation Process in Digital Logic Circuits. - Xiangning Yang; Eric F. Weglarz; Kewal K. Saluja (VLSI Design, 2007)

Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. - Masato Nakasato; Satoshi Ohtake; Kewal K. Saluja; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2007)

A Novel ATPG Method for Capture Power Reduction during Scan Testing. - Xiaoqing Wen; Seiji Kajihara; Kohei Miyase; Tatsuya Suzuki; Kewal K. Saluja; Laung-Terng Wang; Kozo Kinoshita (IEICE Trans. Inf. Syst., 2007)

Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. - Yoshiyuki Nakamura; Thomas Clouqueur; Kewal K. Saluja; Hideo Fujiwara (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (ATS, 2008)

An accurate flip-flop selection technique for reducing logic SER. - Eric L. Hill; Mikko H. Lipasti; Kewal K. Saluja (DSN, 2008)

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. - Xiaoqing Wen; Kohei Miyase; Seiji Kajihara; Hiroshi Furukawa; Yuta Yamato; Atsushi Takashima; Kenji Noda; Hideaki Ito; Kazumi Hatayama; Takashi Aikyo; Kewal K. Saluja (ETS, 2008)

Moments Based Blind Calibration in Mobile Sensor Networks. - Chao Wang; Parameswaran Ramanathan; Kewal K. Saluja (ICC, 2008)

Implementing high availability memory with a duplication cache. - Nidhi Aggarwal; James E. Smith 001; Kewal K. Saluja; Norman P. Jouppi; Parthasarathy Ranganathan (MICRO, 2008)

Calibrating Nonlinear Mobile Sensors. - Chao Wang; Parmesh Ramanathan; Kewal K. Saluja (SECON, 2008)

Testing Flash Memories for Tunnel Oxide Defects. - Mohammad Gh. Mohammad; Kewal K. Saluja (VLSI Design, 2008)

NBTI Degradation: A Problem or a Scare? - Kewal K. Saluja; Shriram Vijayakumar; Warin Sootkaneung; Xaingning Yang (VLSI Design, 2008)

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. - Xiaoqing Wen; Kohei Miyase; Tatsuya Suzuki; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja; Kozo Kinoshita (J. Electron. Test., 2008)

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Inf. Syst., 2008)

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Analysis and test procedures for NOR flash memory defects. - Mohammad Gh. Mohammad; Kewal K. Saluja (Microelectron. Reliab., 2008)

Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies. - Chunhua Yao; Kewal K. Saluja; Parameswaran Ramanathan (Asian Test Symposium, 2009)

DX-compactor: distributed X-compaction for SoCs. - Reshma C. Jumani; Niraj Bharatkumar Jain; Virendra Singh; Kewal K. Saluja (ACM Great Lakes Symposium on VLSI, 2009)

Power and thermal constrained test scheduling. - Chunhua Yao; Kewal K. Saluja; Parameswaran Ramanathan (ITC, 2009)

Blindly Calibrating Mobile Sensors Using Piecewise Linear Functions. - Chao Wang; Parmesh Ramanathan; Kewal K. Saluja (SECON, 2009)

WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements. - Chunhua Yao; Kewal K. Saluja; Abhishek A. Sinkar (VLSI Design, 2009)

False Path Aware Timing Yield Estimation under Variability. - Lin Xie; Azadeh Davoodi; Kewal K. Saluja; Abhishek A. Sinkar (VTS, 2009)

Low-Area Wrapper Cell Design for Hierarchical SoC Testing. - Kyuchull Kim; Kewal K. Saluja (J. Electron. Test., 2009)

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Sin-ya Kobayashi; Yuzo Takamatsu (Inf. Media Technol., 2009)

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Modeling Detection Latency with Collaborative Mobile Sensing Architecture. - Tai-Lin Chin; Parameswaran Ramanathan; Kewal K. Saluja (IEEE Trans. Computers, 2009)

Controlling Peak Power Consumption for Scan Based Multiple Weighted Random BIST. - Hiroshi Yokoyama; Hideo Tamamoto; Kewal K. Saluja (Asian Test Symposium, 2010)

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. - Lin Xie; Azadeh Davoodi; Kewal K. Saluja (DAC, 2010)

Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. - Pramod Subramanyan; Virendra Singh; Kewal K. Saluja; Erik Larsson (DATE, 2010)

Gate input reconfiguration for combating soft errors in combinational circuits. - Warin Sootkaneung; Kewal K. Saluja (DSN Workshops, 2010)

Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding. - Pramod Subramanyan; Virendra Singh; Kewal K. Saluja; Erik Larsson (DSN, 2010)

Modified T-Flip-Flop based scan cell for RAS. - Raghavendra Adiga; Gandhi Arpit; Virendra Singh; Kewal K. Saluja; Adit D. Singh (ETS, 2010)

SEU tolerant SRAM for FPGA applications. - Sudipta Sarkar; Anubhav Adak; Virendra Singh; Kewal K. Saluja; Masahiro Fujita (FPT, 2010)

Energy-efficient redundant execution for chip multiprocessors. - Pramod Subramanyan; Virendra Singh; Kewal K. Saluja; Erik Larsson (ACM Great Lakes Symposium on VLSI, 2010)

Test application time minimization for RAS using basis optimization of column decoder. - A. Abhishek; Amanulla Khan; Virendra Singh; Kewal K. Saluja; Adit D. Singh (ISCAS, 2010)

Detection of inter-port bridging faults in dual-port memories. - Ho-Yong Choi; Kewal K. Saluja (ISCAS, 2010)

On techniques for handling soft errors in digital circuits. - Warin Sootkaneung; Kewal K. Saluja (ITC, 2010)

Connected Barrier Coverage on a Narrow Band: Analysis and Deployment. - Yen-Ting Lin; Kewal K. Saluja; Parameswaran Ramanathan (SECON, 2010)

On Minimization of Test Application Time for RAS. - Raghavendra Adiga; Gandhi Arpit; Virendra Singh; Kewal K. Saluja; Hideo Fujiwara; Adit D. Singh (VLSI Design, 2010)

Collaborative patrolling for target detection using mobile sensor networks. - Tai-Lin Chin; Parameswaran Ramanathan; Kewal K. Saluja (WCSP, 2010)

A Study of Capture-Safe Test Generation Flow for At-Speed Testing. - Kohei Miyase; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Atsushi Takashima; Hiroshi Furukawa; Kenji Noda; Hideaki Ito; Kazumi Hatayama; Takashi Aikyo; Kewal K. Saluja (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Modeling latency - lifetime trade-off for target detection in mobile sensor networks. - Chao Wang; Parameswaran Ramanathan; Kewal K. Saluja (ACM Trans. Sens. Networks, 2010)

Fault simulation and test generation for clock delay faults. - Yoshinobu Higami; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (ASP-DAC, 2011)

On Detecting Transition Faults in the Presence of Clock Delay Faults. - Yoshinobu Higami; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (Asian Test Symposium, 2011)

Temperature Dependent Test Scheduling for Multi-core System-on-Chip. - Chunhua Yao; Kewal K. Saluja; Parameswaran Ramanathan (Asian Test Symposium, 2011)

Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations. - Tsuyoshi Iwagaki; Kewal K. Saluja (DDECS, 2011)

Enhancement of Clock Delay Faults Testing. - Yoshinobu Higami; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (ETS, 2011)

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. - Pramod Subramanyan; Virendra Singh; Kewal K. Saluja; Erik Larsson (ICCD, 2011)

A low cost approach to calibrate on-chip thermal sensors. - Krishna Bharath; Chunhua Yao; Nam Sung Kim; Parameswaran Ramanathan; Kewal K. Saluja (ISQED, 2011)

SEU tolerant SRAM cell. - Sudipta Sarkar; Anubhav Adak; Virendra Singh; Kewal K. Saluja; Masahiro Fujita (ISQED, 2011)

Soft error reduction through gate input dependent weighted sizing in combinational circuits. - Warin Sootkaneung; Kewal K. Saluja (ISQED, 2011)

Thermal-Aware Test Scheduling Using On-chip Temperature Sensors. - Chunhua Yao; Kewal K. Saluja; Parameswaran Ramanathan (VLSI Design, 2011)

Adaptive cost efficient deployment strategy for homogeneous wireless camera sensors. - Yen-Ting Lin; Kewal K. Saluja; Seapahn Megerian (Ad Hoc Networks, 2011)

Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach. - Chunhua Yao; Kewal K. Saluja; Parmesh Ramanathan (J. Electron. Test., 2011)

Routing TCP Flows in Underwater Mesh Networks. - Chin-Ya Huang; Parameswaran Ramanathan; Kewal K. Saluja (IEEE J. Sel. Areas Commun., 2011)

Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies. - Chunhua Yao; Kewal K. Saluja; Parameswaran Ramanathan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits. - Spencer K. Millican; Kewal K. Saluja (Asian Test Symposium, 2012)

Diagnosis for Bridging Faults on Clock Lines. - Yoshinobu Higami; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (PRDC, 2012)

Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate. - Warin Sootkaneung; Kewal K. Saluja (VLSI Design, 2012)

Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling. - Spencer K. Millican; Kewal K. Saluja (Asian Test Symposium, 2013)

Diagnosing Resistive Open Faults Using Small Delay Fault Simulation. - Koji Yamazaki; Toshiyuki Tsutsumi; Hiroshi Takahashi; Yoshinobu Higami; Hironobu Yotsuyanagi; Masaki Hashizume; Kewal K. Saluja (Asian Test Symposium, 2013)

DRMA: dynamically reconfigurable MPSoC architecture. - Lawrance Zhang; Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran; Roshan G. Ragel; Swarnalatha Radhakrishnan; Kewal K. Saluja (ACM Great Lakes Symposium on VLSI, 2013)

Privacy Assurances in Multiple Data-Aggregation Transactions. - Kim T. Le; Parmesh Ramanathan; Kewal K. Saluja (ICISC, 2013)

On thermal utilization of periodic task sets in uni-processor systems. - Rehan Ahmed; Parameswaran Ramanathan; Kewal K. Saluja (RTCSA, 2013)

Scheduling Aperiodic Tasks in Next Generation Embedded Real-Time Systems. - Rehan Ahmed; Parameswaran Ramanathan; Kewal K. Saluja; Chunhua Yao (VLSI Design, 2013)

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment. - Yoshinobu Higami; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (IEICE Trans. Inf. Syst., 2013)

Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks. - Rehan Ahmed; Parameswaran Ramanathan; Kewal K. Saluja (ECRTS, 2014)

Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults. - Yoshinobu Higami; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (ISVLSI, 2014)

Temperature Minimization Using Power Redistribution in Embedded Systems. - Rehan Ahmed; Parameswaran Ramanathan; Kewal K. Saluja (VLSID, 2014)

CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities. - Spencer K. Millican; Parameswaran Ramanathan; Kewal K. Saluja (VLSID, 2014)

A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits. - Spencer K. Millican; Kewal K. Saluja (VLSID, 2014)

Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling. - Spencer K. Millican; Kewal K. Saluja (J. Electron. Test., 2014)

A Methodology for Identifying High Timing Variability Paths in Complex Designs. - Virendra Singh; Adit D. Singh; Kewal K. Saluja (ATS, 2015)

Privacy Assurance in Data-Aggregation for Multiple MAX Transactions. - Kim T. Le; Parmesh Ramanathan; Kewal K. Saluja (COMPSAC Workshops, 2015)

Transient Fault Resilient QR Factorization on GPUs. - Felix Loh; Parameswaran Ramanathan; Kewal K. Saluja (FTXS@HPDC, 2015)

Diagnosis of Delay Faults Considering Hazards. - Yoshinobu Higami; Senling Wang; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (ISVLSI, 2015)

Thermal Extension of the Total Bandwidth Server. - Rehan Ahmed; Ayoosh Bansal; Bhuvana Kakunoori; Parameswaran Ramanathan; Kewal K. Saluja (VLSID, 2015)

Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints. - Spencer K. Millican; Kewal K. Saluja (VLSID, 2015)

Crypt-Delay: Encrypting IP Cores with Capabilities for Gate-level Logic and Delay Simulations. - Parameswaran Ramanathan; Kewal K. Saluja (ATS, 2016)

Fault Tolerance through Invariant Checking for Iterative Solvers. - Felix Loh; Kewal K. Saluja; Parameswaran Ramanathan (VLSID, 2016)

Digital Testing - Basics to Advanced Research Issues. - Kewal K. Saluja (VLSID, 2016)

Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays. - Yoshinobu Higami; Senling Wang; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (IPSJ Trans. Syst. LSI Des. Methodol., 2016)

Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks Under Fluid Scheduling Model. - Rehan Ahmed; Parameswaran Ramanathan; Kewal K. Saluja (ACM Trans. Embed. Comput. Syst., 2016)

Exploiting path delay test generation to develop better TDF tests for small delay defects. - Ankush Srivastava; Adit D. Singh; Virendra Singh; Kewal K. Saluja (ITC, 2017)

Identifying high variability speed-limiting paths under aging. - Ankush Srivastava; Virendra Singh; Adit D. Singh; Kewal K. Saluja (LATS, 2017)

A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. - Ankush Srivastava; Virendra Singh; Adit D. Singh; Kewal K. Saluja (J. Electron. Test., 2017)

A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line. - Yoshinobu Higami; Senling Wang; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (IEICE Trans. Inf. Syst., 2017)

Fault Tolerant Cholesky Factorization on GPUs. - Felix Loh; Kewal K. Saluja; Parameswaran Ramanathan (FTXS@SC, 2018)

Fault Tolerance through Invariant Checking for the Lanczos Eigensolver. - Felix Loh; Kewal K. Saluja; Parameswaran Ramanathan (VLSID, 2020)

Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method. - Felix Loh; Kewal K. Saluja; Parameswaran Ramanathan (J. Electron. Test., 2021)