A 20 Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter. - Byungho Min; Keytaek Lee; Samuel Palermo (Microelectron. J., 2012)

A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications. - Ehsan Zhian Tabasy; Ayman Shafik; Keytaek Lee; Sebastian Hoyos; Samuel Palermo (IEEE J. Solid State Circuits, 2014)

3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS. - Ayman Shafik; Ehsan Zhian Tabasy; Shengchang Cai; Keytaek Lee; Sebastian Hoyos; Samuel Palermo (ISSCC, 2015)

CMOS ADC-based receivers for high-speed electrical and optical links. - Samuel Palermo; Sebastian Hoyos; Ayman Shafik; Ehsan Zhian Tabasy; Shengchang Cai; Shiva Kiran; Keytaek Lee (IEEE Commun. Mag., 2016)

A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization. - Ayman Shafik; Ehsan Zhian Tabasy; Shengchang Cai; Keytaek Lee; Sebastian Hoyos; Samuel Palermo (IEEE J. Solid State Circuits, 2016)