Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA. - Khai-Minh Ma; Duc-Hung Le; Cong-Kha Pham; Trong-Thuc Hoang (Future Internet, 2023)

Implementing a Secure Boot System on a 32-Bit RISC-V CPU on FPGA. - Quoc-Dang Tran; Khai-Minh Ma; Trong-Tu Bui; Cong-Kha Pham; Duc-Hung Le (RIVF, 2024)

Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System. - Binh Kieu-Do-Nguyen; Khai-Duy Nguyen; Nguyen The Binh; Khai-Minh Ma; Tri Duc Ta; Duc-Hung Le; Cong-Kha Pham; Trong-Thuc Hoang (IEEE Access, 2024)