Statistical timing analysis with two-sided constraints. - Khaled R. Heloue; Farid N. Najm (ICCAD, 2005)

Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. - Khaled R. Heloue; Navid Azizi; Farid N. Najm (DAC, 2007)

Parameterized timing analysis with general delay models and arbitrary variation sources. - Khaled R. Heloue; Farid N. Najm (DAC, 2008)

Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models. - Khaled R. Heloue; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Clock skew optimization via wiresizing for timing sign-off covering all process corners. - Sari Onaissi; Khaled R. Heloue; Farid N. Najm (DAC, 2009)

Quantifying robustness metrics in parameterized static timing analysis. - Khaled R. Heloue; Chandramouli V. Kashyap; Farid N. Najm (ICCAD, 2009)

PSTA-based branch and bound approach to the silicon speedpath isolation problem. - Sari Onaissi; Khaled R. Heloue; Farid N. Najm (ICCAD, 2009)

Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation. - Khaled R. Heloue; Navid Azizi; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths. - Khaled R. Heloue; Sari Onaissi; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)