A novel low-leakage 8T differential SRAM cell. - Khawar Sarfraz (VLSI-SoC, 2011)

Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins. - Khawar Sarfraz; Volkan Kursun (ISVLSI, 2013)

Nanoscale register file circuit design - Challenges and opportunities. - Khawar Sarfraz; Mansun Chan (ASICON, 2015)

A 65nm 3.2GHz 44.2mW Low-Vt register file with robust low-capacitance dynamic local bitlines. - Khawar Sarfraz; Mansun Chan (ESSCIRC, 2015)

A voltage-scalable zero-delay-overhead scheme for standby power reduction in dynamic register files. - Khawar Sarfraz; Mansun Chan (MWSCAS, 2016)

A compact low-power 4-port register file with grounded write bitlines and single-ended read operations. - Khawar Sarfraz; Mansun Chan (Integr., 2016)

A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS. - Khawar Sarfraz; Jin He 003; Mansun Chan (IEEE J. Solid State Circuits, 2017)

A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS. - Khawar Sarfraz; Mansun Chan (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm. - Danfeng Xu; Yu Kou; Paul Lai; Zichuan Cheng; Tze Yin Cheung; Larry Moser; Yang Zhang; Xiaolong Liu; Man Pio Lam; Haikun Jia; Quan Pan 002; Wing Hong Szeto; et al. (ISSCC, 2021)

An Efficient 6TP SRAM-Based CIM Macro With Column ADCs for Binarized Neural Networks. - Ikramullah Shah; Khawar Sarfraz; Mansun Chan (IEEE Trans. Circuits Syst. II Express Briefs, 2024)