A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm. - Raul Cernea; Long Pham; Farookh Moogat; Siu Lung Chan; Binh Le; Yan Li; Shouchang Tsao; Taiyuan Tseng; Khanh Nguyen; Jason Li 001; Jayson Hu; Jong Park; et al. (ISSCC, 2008)

A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate. - Yan Li; Seungpil Lee; Yupin Fong; Feng Pan; Tien-Chien Kuo; Jong Park; Tapan Samaddar; Hao Nguyen; Man Mui; Khin Htoo; Teruhiko Kamei; Masaaki Higashitani; et al. (ISSCC, 2008)

A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology. - Raul Cernea; Long Pham; Farookh Moogat; Siu Lung Chan; Binh Le; Yan Li; Shouchang Tsao; Taiyuan Tseng; Khanh Nguyen; Jason Li 001; Jayson Hu; Jonghak Yuh; et al. (IEEE J. Solid State Circuits, 2009)

A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate. - Yan Li; Seungpil Lee; Yupin Fong; Feng Pan; Tien-Chien Kuo; Jongmin Park; Tapan Samaddar; Hao Nguyen; Man Mui; Khin Htoo; Teruhiko Kamei; Masaaki Higashitani; et al. (IEEE J. Solid State Circuits, 2009)

128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode. - Yan Li; Seungpil Lee; Ken Oowada; Hao Nguyen; Qui Nguyen; Nima Mokhlesi; Cynthia Hsu; Jason Li 001; Venky Ramachandra; Teruhiko Kamei; Masaaki Higashitani; Tuan Pham; et al. (ISSCC, 2012)

A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os. - Kosuke Yanagidaira; Mario Sako; Yasuhiro Hirashima; Junya Matsuno; Yumi Higashi; Yutaka Shimizu; Akihiro Imamoto; Kazuaki Kawaguchi; Koji Tabata; Takeshi Nakano; Yusuke Ochi; Hiroaki Hoshino; et al. (ISSCC, 2025)