Digital phase tightening for millimeter-wave imaging. - Khoa Minh Nguyen; Anthony J. Accardi; Helen Kim; Gregory W. Wornell; Charles G. Sodini (CICC, 2010)

Key receiver circuits for digital beamforming in MMW imaging. - Khoa Minh Nguyen (2011)

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver. - Hasnain Lakdawala; Mark Schaecher; Chang-Tsung Fu; Rahul Dilip Limaye; Jon Duster; Yulin Tan; Ajay Balankutty; Erkan Alpman; Chun C. Lee; Khoa Minh Nguyen; Hyung-Jin Lee; Ashoke Ravi; et al. (IEEE J. Solid State Circuits, 2013)

19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS. - Kuan-Yueh James Shen; Syed Feruz Syed Farooq; Yongping Fan; Khoa Minh Nguyen; Qi Wang; Amr Elshazly; Nasser A. Kurd (ISSCC, 2016)

A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O. - William Y. Li; Hyung Seok Kim; Kailash Chandrashekar; Khoa Minh Nguyen; Ashoke Ravi (ISLPED, 2017)

13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications. - Paolo Madoglio; Hongtao Xu; Kailash Chandrashekar; Luis Cuellar 001; Muhammad Faisal; Yee William Li; Hyung Seok Kim; Khoa Minh Nguyen; Yulin Tan; Brent R. Carlton; Vaibhav A. Vaidya; Yanjie Wang; et al. (ISSCC, 2017)

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS. - Kuan-Yueh James Shen; Syed Feruz Syed Farooq; Yongping Fan; Khoa Minh Nguyen; Qi Wang; Mark Neidengard; Nasser A. Kurd; Amr Elshazly (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)