Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack. - Khoirom Johnson Singh; Anand Bulusu; Sudeb Dasgupta (ISCAS, 2021)

Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric. - Khoirom Johnson Singh; Lomash Chandra Acharya; Anand Bulusu; Sudeb Dasgupta (ISCAS, 2022)

An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime. - Mahipal Dargupally; Lomash Chandra Acharya; Khoirom Johnson Singh; Neha Gupta; Arvind K. Sharma; Sudeb Dasgupta; Anand Bulusu (APCCAS, 2023)

Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure. - Lomash Chandra Acharya; Anubhav Kumar; Khoirom Johnson Singh; Neha Gupta; Nayakanti Sai Shabarish; Neeraj Mishra; Mahipal Dargupally; Arvind Kumar Sharma; Venkatraman Ramakrishnan; Ajoy Mandal; Sudeb Dasgupta; Anand Bulusu (SMACD, 2023)

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort. - Lomash Chandra Acharya; Arvind Kumar Sharma; Neeraj Mishra; Khoirom Johnson Singh; Mahipal Dargupally; Nayakanti Sai Shabarish; Ajoy Mandal; Venkatraman Ramakrishnan; Sudeb Dasgupta; Anand Bulusu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations. - Khoirom Johnson Singh; Lomash Chandra Acharya; Anand Bulusu; Sudeb Dasgupta (Microelectron. J., 2023)

Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis. - Lomash Chandra Acharya; Arvind K. Sharma; Neeraj Mishra; Khoirom Johnson Singh; Mahipal Dargupally; Neha Gupta; Nayakanti Sai Shabarish; Ajoy Mandal; Venkatraman Ramakrishnan; Sudeb Dasgupta; Anand Bulusu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)