A new hardware efficient, low power FIR digital filter implementation approach. - Khosrov Dabbagh-Sadeghipour; Ali Aghagolzadeh (ICECS, 2003)

A new wideband, high-linear passive Sample and Hold structure suitable for high-speed, high-resolution ADCs. - Khosrov Dabbagh-Sadeghipour (APCCAS, 2008)

A new FPGA-based postprocessor architecture for channel mismatch correction of time interleaved ADCS. - Asgar Abbaszadeh; Khosrov Dabbagh-Sadeghipour (SiPS, 2009)

A new offset cancelled latch comparator for high-speed, low-power ADCs. - Khosrov Dabbagh-Sadeghipour (APCCAS, 2010)

A new hardware efficient reconfigurable fir filter architecture suitable for FPGA applications. - Asgar Abbaszadeh; Anasystem Azerbaijan; Khosrov Dabbagh-Sadeghipour (DSP, 2011)

Efficient realization of reconfigurable FIR filter using the new coefficient representation. - Khosrov Dabbagh-Sadeghipour; Asgar Abbaszadeh (IEICE Electron. Express, 2011)

An accurate track-and-latch comparator. - Khosrov Dabbagh-Sadeghipour (IEICE Electron. Express, 2012)

Design of a sample-and-hold analog front end for a 56Gb/s PAM-4 receiver using 65nm CMOS. - Khosrov Dabbagh-Sadeghipour; Paul D. Townsend; Peter Ossieur (ISCAS, 2015)

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications. - Meysam M. Khanghah; Khosrov Dabbagh-Sadeghipour; Denis Kelly; Cleitus Antony; Peter Ossieur; Paul D. Townsend (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)