A clock boosting scheme for low voltage circuits. - Amirehsan Behradfar; Saeed Zeinolabedinzadeh; Khosrow Hajsadeghi (ICECS, 2008)

A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria. - Roghayeh Saeidi; Mohammad Sharifkhani; Khosrow Hajsadeghi (ISCAS, 2011)

New Operational Transconductance Amplifiers using current boosting. - Mehdi Noormohammadi; Vahid Khojasteh Lazarjan; Khosrow Hajsadeghi (MWSCAS, 2012)

A novel low power 8T-cell sub-threshold SRAM with improved read-SNM. - Sina Hassanzadeh; Milad Zamani; Khosrow Hajsadeghi; Roghayeh Saeidi (DTIS, 2013)

A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM. - Milad Zamani; Sina Hassanzadeh; Khosrow Hajsadeghi; Roghayeh Saeidi (DTIS, 2013)

12 bits, 40MS/s, low power pipelined SAR ADC. - Vahid Khojasteh Lazarjan; Khosrow Hajsadeghi (MWSCAS, 2014)

Fine logarithmic adaptive soft morphological algorithm for synthetic aperture radar image segmentation. - Mohaddeseh Koosha; Khosrow Hajsadeghi; Mohammad Koosha (IET Image Process., 2014)

A Subthreshold Symmetric SRAM Cell With High Read Stability. - Roghayeh Saeidi; Mohammad Sharifkhani; Khosrow Hajsadeghi (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell. - Roghayeh Saeidi; Mohammad Sharifkhani; Khosrow Hajsadeghi (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application. - Hasan Molaei; Ata Khorami; Mohammad S. Eslampanah Sendi; Khosrow Hajsadeghi (ICECS, 2015)

A wide dynamic range low power 2× time amplifier using current subtraction scheme. - Hasan Molaei; Ata Khorami; Khosrow Hajsadeghi (ISCAS, 2016)

A low power high resolution time to digital converter for ADPLL application. - Hasan Molaei; Khosrow Hajsadeghi (MWSCAS, 2016)

Circuit design to improve security of telecommunication devices. - Hengameh Bahrami; Khosrow Hajsadeghi (CCWC, 2017)

A low-power comparator-reduced flash ADC using dynamic comparators. - Hasan Molaei; Khosrow Hajsadeghi (ICECS, 2017)

A 1.6 ps 7 b time to digital converter in 0.18 µm CMOS technology. - Hasan Molaei; Khosrow Hajsadeghi (Microelectron. J., 2017)

Design of low power comparator-reduced hybrid ADC. - Hasan Molaei; Khosrow Hajsadeghi; Ata Khorami (Microelectron. J., 2018)

A 5.3-ps, 8-b Time to Digital Converter Using a New Gain-Reconfigurable Time Amplifier. - Hasan Molaei; Khosrow Hajsadeghi (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Predicting scientific research trends based on link prediction in keyword networks. - Saman Behrouzi; Zahra Shafaeipour Sarmoor; Khosrow Hajsadeghi; Kaveh Kavousi (J. Informetrics, 2020)

A Novel Design of 16-bit Multi-Mode 4-Channel Time-Interleaved Delta-Sigma Digital-to-Analog Converter. - Abolfazl Roshanpanah; Pooya Torkzadeh; Khosrow Hajsadeghi; Massoud Dousti (J. Circuits Syst. Comput., 2024)

Design and Implementation of a 16-bit Multi-mode 4-Channel Time-Interleaved Delta-Sigma Modulator with SNDR > 106 dB and DCE Compensation Based on FPGA. - Abolfazl Roshanpanah; Pooya Torkzadeh; Khosrow Hajsadeghi; Massoud Dousti (Circuits Syst. Signal Process., 2025)