SAT based low power binding to reduce switching activity. - Khushbu Chandrakar; Suchismita Roy (IC3, 2013)

Power Optimization Techniques for High-Level Designs Using Multiple Voltage Components for Low Power Consumption. - Khushbu Chandrakar; Sudeshna Kundu; Suchismita Roy (J. Low Power Electron., 2018)

A SAT-Based Methodology for Effective Clock Gating for Power Minimization. - Khushbu Chandrakar; Suchismita Roy (J. Circuits Syst. Comput., 2019)