A Novel Scheme of Data Hiding for Color Images in Spatial Domain with High Capacity of Embedding. - Nagaraj V. Dharwadkar; Khyamling Parane; Shivananda R. Poojara (ICCCT, 2015)

Cache analysis and software optimizations for faster on-chip network simulations. - Khyamling Parane; Prabhu B. M. Prasad; Basavaraj Talawar (ICIIS, 2016)

Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA. - G. S. Sangeetha; Vignesh Radhakrishnan; Prabhu B. M. Prasad; Khyamling Parane; Basavaraj Talawar (ISED, 2018)

YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs. - Khyamling Parane; Basavaraj Talawar; Prabhu B. M. Prasad (VLSID, 2018)

High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs. - Prabhu B. M. Prasad; Khyamling Parane; Basavaraj Talawar (ISQED, 2019)

Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA. - Khyamling Parane; Prabhu B. M. Prasad; Basavaraj Talawar (VLSI-DAT, 2019)

High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks. - Prabhu B. M. Prasad; Khyamling Parane; Basavaraj Talawar (VLSI-DAT, 2019)

YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs. - Khyamling Parane; Prabhu B. M. Prasad; Basavaraj Talawar (J. Circuits Syst. Comput., 2019)

Analysis of cache behaviour and software optimizations for faster on-chip network simulations. - Prabhu B. M. Prasad; Khyamling Parane; Basavaraj Talawar (Int. J. Syst. Assur. Eng. Manag., 2019)

An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks. - Prabhu B. M. Prasad; Khyamling Parane; Basavaraj Talawar (Circuits Syst. Signal Process., 2020)

LBNoC: Design of Low-latency Router Architecture with Lookahead Bypass for Network-on-Chip Using FPGA. - Khyamling Parane; Prabhu B. M. Prasad; Basavaraj Talawar (ACM Trans. Design Autom. Electr. Syst., 2020)

P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA. - Khyamling Parane; Prabhu B. M. Prasad; Basavaraj Talawar (Wirel. Pers. Commun., 2020)

FPGA friendly NoC simulation acceleration framework employing the hard blocks. - Prabhu B. M. Prasad; Khyamling Parane; Basavaraj Talawar (Computing, 2021)