A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. - Ki Chul Chun; Pulkit Jain; Chris H. Kim (ISLPED, 2009)

Logic-compatible embedded DRAM design for memory intensive low power systems. - Ki Chul Chun; Pulkit Jain; Chris H. Kim (ISCAS, 2010)

Variation aware performance analysis of gain cell embedded DRAMs. - Wei Zhang 032; Ki Chul Chun; Chris H. Kim (ISLPED, 2010)

A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies. - Ki Chul Chun; Wei Zhang 032; Pulkit Jain; Chris H. Kim (ISSCC, 2011)

A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches. - Ki Chul Chun; Pulkit Jain; Jung-Hwa Lee; Chris H. Kim (IEEE J. Solid State Circuits, 2011)

A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme. - Seung-Hwan Song; Ki Chul Chun; Chris H. Kim (VLSIC, 2012)

A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor. - Ki Chul Chun; Wei Zhang 032; Pulkit Jain; Chris H. Kim (IEEE J. Solid State Circuits, 2012)

A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches. - Ki Chul Chun; Pulkit Jain; Tae-Ho Kim; Chris H. Kim (IEEE J. Solid State Circuits, 2012)

A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applications. - Seung-Hwan Song; Ki Chul Chun; Chris H. Kim (CICC, 2013)

A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory. - Ki Chul Chun; Hui Zhao; Jonathan D. Harms; Tony Tae-Hyoung Kim; Jianping Wang 006; Chris H. Kim (IEEE J. Solid State Circuits, 2013)

A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme. - Seung-Hwan Song; Ki Chul Chun; Chris H. Kim (IEEE J. Solid State Circuits, 2013)

A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode. - Wei Zhang 032; Ki Chul Chun; Chris H. Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications. - Seung-Hwan Song; Ki Chul Chun; Chris H. Kim (IEEE J. Solid State Circuits, 2014)

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. - Ki Chul Chun; Yonggyu Chu; Jin-Seok Heo; Tae-Sung Kim; Soohwan Kim; Hui-Kap Yang; Mi-Jo Kim; Chang-Kyo Lee; Ju-Hwan Kim; Hyunchul Yoon; Chang-Ho Shin; Sang-uhn Cha; et al. (ISSCC, 2018)

22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme. - Chi-Sung Oh; Ki Chul Chun; Young-Yong Byun; Yong-Ki Kim; So-Young Kim; Yesin Ryu; Jaewon Park; Sinho Kim; Sang-uhn Cha; Dong-Hak Shin; Jungyu Lee 002; Jong-Pil Son; et al. (ISSCC, 2020)

An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process. - Jaewon Park; Jae Hoon Lee; Sang-Kil Park; Ki Chul Chun; Kyomin Sohn; Sungho Kang 001 (IEEE Access, 2021)

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme. - Ki Chul Chun; Yong-Ki Kim; Yesin Ryu; Jaewon Park; Chi Sung Oh; Young-Yong Byun; So-Young Kim; Dong-Hak Shin; Jun Gyu Lee 002; Byung-Kyu Ho; Min-Sang Park; Seong-Jin Cho; et al. (IEEE J. Solid State Circuits, 2021)