VIRON: An Annotation-Based Video Information Retrieval System. - Ki-Wook Kim; Ki-Byoung Kim; Hyoung-Joo Kim 001 (COMPSAC, 1996)

Logic Transformation for Low Power Synthesis. - Ki-Wook Kim; Sung-Mo Kang; TingTing Hwang; C. L. Liu 001 (DATE, 1999)

Implication graph based domino logic synthesis. - Ki-Wook Kim; C. L. Liu 001; Sung-Mo Kang (ICCAD, 1999)

Domino logic synthesis minimizing crosstalk. - Ki-Wook Kim; Unni Narayanan; Sung-Mo Kang (DAC, 2000)

Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. - Ki-Wook Kim; Kwang-Hyun Baek; Naresh R. Shanbhag; C. L. Liu 001; Sung-Mo Kang (ICCAD, 2000)

Noise-aware power optimization for on-chip interconnect. - Ki-Wook Kim; Seong-Ook Jung; Unni Narayanan; C. L. Liu 001; Sung-Mo Kang (ISLPED, 2000)

Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. - Ki-Wook Kim; Seong-Ook Jung; Prashant Saxena; C. L. Liu 001; Sung-Mo Kang (DAC, 2001)

Transistor sizing for reliable domino logic design in dual threshold voltage technologies. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (ACM Great Lakes Symposium on VLSI, 2001)

Noise constrained power optimization for dual VT domino logic. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (ISCAS (4), 2001)

Skew-tolerant high-speed (STHS) domino logic. - Seong-Ook Jung; Seung-Moon Yoo; Ki-Wook Kim; Sung-Mo Kang (ISCAS (4), 2001)

Coupling-aware minimum delay optimization for domino logic circuits. - Ki-Wook Kim; Seong-Ook Jung; Sung-Mo Kang (ISCAS (5), 2001)

Energy-efficient skewed static logic design with dual Vt. - Chulwoo Kim; Ki-Wook Kim; Sung-Mo Kang (ISCAS (4), 2001)

Crosstalk noise minimization in domino logic design. - Ki-Wook Kim; Sung-Mo Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Reliable Low -Power Solution for High -Performance VLSI Circuit Design - Ki-Wook Kim (2001)

Low-swing clock domino logic incorporating dual supply and dual threshold voltages. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (DAC, 2002)

VeriCDF: a new verification methodology for charged device failures. - Jaesik Lee; Ki-Wook Kim; Sung-Mo Kang (DAC, 2002)

Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (DATE, 2002)

Coupling-aware high-level interconnect synthesis for low power. - Chun-Gi Lyuh; Taewhan Kim 001; Ki-Wook Kim (ICCAD, 2002)

Optimal Timing for Skew-Tolerant High-Speed Domino Logic. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (ISVLSI, 2002)

Domino logic synthesis based on implication graph. - Ki-Wook Kim; Taewhan Kim 001; C. L. Liu 001; Sung-Mo Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Logic transformation for low-power synthesis. - Ki-Wook Kim; Taewhan Kim 001; TingTing Hwang; Sung-Mo Kang; C. L. Liu 001 (ACM Trans. Design Autom. Electr. Syst., 2002)

Noise constrained transistor sizing and power optimization for dual Vst domino logic. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Timing constraints for domino logic gates with timing-dependent keepers. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Chip-level charged-device modeling and simulation in CMOS integrated circuits. - Jaesik Lee; Ki-Wook Kim; Yoonjong Huh; Peter Bendix; Sung-Mo Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Minimum delay optimization for domino circuits - a coupling-aware approach. - Ki-Wook Kim; Seong-Ook Jung; Taewhan Kim 001; Sung-Mo Kang (ACM Trans. Design Autom. Electr. Syst., 2003)

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. - Ki-Wook Kim; Seong-Ook Jung; Taewhan Kim 001; Prashant Saxena; C. L. Liu 001; S.-M. S. Kang (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Noise-aware interconnect power optimization in domino logic synthesis. - Ki-Wook Kim; Seong-Ook Jung; Unni Narayanan; C. L. Liu 001; Sung-Mo Kang (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Energy-efficient skewed static logic with dual Vt: design and synthesis. - Chulwoo Kim; Ki-Wook Kim; Sung-Mo Kang (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Coupling-aware high-level interconnect synthesis [IC layout]. - Chun-Gi Lyuh; Taewhan Kim 001; Ki-Wook Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Distributed cluster head election algorithm using local energy estimation. - Ki-Wook Kim; Kwang-Ryoul Kim; Sung-Gi Min (ICHIT, 2009)

A programmable data plane to support in-network data processing in software-defined IoT. - Ki-Wook Kim; Sung-Gi Min; Youn-Hee Han (ICTC, 2017)

An Authentication and Key Management Mechanism for Resource Constrained Devices in IEEE 802.11-based IoT Access Networks. - Ki-Wook Kim; Youn-Hee Han; Sung-Gi Min (Sensors, 2017)

In-Network Data Processing in Software-Defined IoT with a Programmable Data Plane. - Ki-Wook Kim; Sung-Gi Min; Youn-Hee Han (Mob. Inf. Syst., 2018)

ScienceIoT: Evolution of the Wireless Infrastructure of KREONET. - Cheonyong Kim; Joobum Kim; Ki-Hyeon Kim; Sang-Kwon Lee; Ki-Wook Kim; Syed Asif Raza Shah; Young-Hoon Goo (Sensors, 2021)