Systolic digital filters with reduced latency - serial implementation. - Christos Gr. Caraiscos; Kiamal Z. Pekmestzi (Int. J. Circuit Theory Appl., 1996)

Hardware compilation using attribute grammars. - George Economakos; George K. Papakonstantinou; Kiamal Z. Pekmestzi; Panayotis Tsanakas (CHARME, 1997)

A scheme for the VLSI implementation of FIR digital filters with reduced latency. - Christos Gr. Caraiscos; Kiamal Z. Pekmestzi (EUSIPCO, 1998)

A systolic serial squarer of continuous operation. - Kiamal Z. Pekmestzi; Nikolaos Moshopoulos; Paraskevas Kalivas (EUSIPCO, 2000)

Constant Number Serial Pipeline Multipliers. - Kiamal Z. Pekmestzi; Paraskevas Kalivas (J. VLSI Signal Process., 2000)

On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms. - Kostas Marinis; Nikos K. Moshopoulos; Fotis Karoubalis; Kiamal Z. Pekmestzi (ISC, 2001)

A Novel Systolic Architecture for Efficient RSA Implementation. - Nikos K. Moshopoulos; Kiamal Z. Pekmestzi (Public Key Cryptography, 2001)

A bit-interleaved systolic architecture for a high-speed RSA system. - Kiamal Z. Pekmestzi; Nikos K. Moshopoulos (Integr., 2001)

A Systolic, High Speed Architecture for an RSA Cryptosystem. - Kiamal Z. Pekmestzi; Nikos K. Moshopoulos (J. VLSI Signal Process., 2002)

Pipeline array implementation of FIR filters. - Paraskevas Kalivas; Paul Bougas; Vassilis Vassilakis; Christos Meletis; Kiamal Z. Pekmestzi (EUSIPCO, 2004)

Low-latency and high-efficiency bit serial-serial multipliers. - Paraskevas Kalivas; Kiamal Z. Pekmestzi; Paul Bougas; Andreas Tsirikos; Kostas Gotsis (EUSIPCO, 2004)

Long Number Bit-Serial Squarers. - E. Chaniotakis; Paraskevas Kalivas; Kiamal Z. Pekmestzi (IEEE Symposium on Computer Arithmetic, 2005)

100% operational efficient bit-serial programmable FIR digital filters. - Paraskevas Kalivas; Andreas Tsirikos; Paul Bougas; Kiamal Z. Pekmestzi (EUSIPCO, 2005)

Novel systolic schemes for serial-parallel multiplication. - Isidoros Sideris; Kostas Anagnostopoulos; Paraskevas Kalivas; Kiamal Z. Pekmestzi (EUSIPCO, 2005)

Pipelined array-based FIR filter folding. - Paul Bougas; Paraskevas Kalivas; Andreas Tsirikos; Kiamal Z. Pekmestzi (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A New Low Latency Parallel FIR Filter Scheme. - Paraskevas Kalivas; Vassilis Vassilakis; Chris Meletis; Kiamal Z. Pekmestzi (J. VLSI Signal Process., 2005)

A Large Scale Adaptable Multiplier for Cryptographic Applications. - Osama Daifallah Al-Khaleel; Christos A. Papachristou; Francis G. Wolff; Kiamal Z. Pekmestzi (AHS, 2006)

FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems. - Osama Daifallah Al-Khaleel; Christos A. Papachristou; Francis G. Wolff; Kiamal Z. Pekmestzi (ICCD, 2006)

Segmentation based design of serial parallel multipliers. - Paul Bougas; Andreas Tsirikos; Kostas Anagnostopoulos; Isidoros Sideris; Kiamal Z. Pekmestzi (ISCAS, 2006)

A cache based stack folding technique for high performance Java processors. - Isidoros Sideris; George Economakos; Kiamal Z. Pekmestzi (JTRES, 2006)

A Reconfigurable Arithmetic Data-path Based On Regular Interconnection. - Sotirios Xydis; George Economakos; Kiamal Z. Pekmestzi (AHS, 2007)

Building embedded DSP applications in a Java modeling framework. - Isidoros Sideris; Dimitris Pilitsos; George Economakos; Kiamal Z. Pekmestzi (EUSIPCO, 2007)

A regular interconnection scheme for efficient mapping of DSP kernels into reconfigurable hardware. - Sotirios Xydis; George Economakos; Kiamal Z. Pekmestzi (EUSIPCO, 2007)

Power-Efficient and Low Latency Implementation of Programmable FIR filters Using Carry-Save Arithmetic. - Dimitris Bekiaris; Isidoros Sideris; George Economakos; Kiamal Z. Pekmestzi (ICECS, 2007)

An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding. - Osama Daifallah Al-Khaleel; Christos A. Papachristou; Francis G. Wolff; Kiamal Z. Pekmestzi (IOLTS, 2007)

Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. - Sotirios Xydis; George Economakos; Kiamal Z. Pekmestzi (ICSAMOS, 2007)

Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility. - Sotirios Xydis; George Economakos; Dimitrios Soudris; Kiamal Z. Pekmestzi (AHS, 2008)

Efficient serial and parallel implementation of programmable fir filters based on the merging technique. - Dimitris Bekiaris; George Economakos; Kiamal Z. Pekmestzi (EUSIPCO, 2008)

A flexible architecture for DSP applications combining high performance arithmetic with small scale configurability. - Sotirios Xydis; Isidoros Sideris; George Economakos; Kiamal Z. Pekmestzi (EUSIPCO, 2008)

A high-speed radix-4 multiplexer-based array multiplier. - Dimitris Bekiaris; Kiamal Z. Pekmestzi; Christos A. Papachristou (ACM Great Lakes Symposium on VLSI, 2008)

A BISR Architecture for Embedded Memories. - Kiamal Z. Pekmestzi; Nicholas Axelos; Isidoros Sideris; Nikos K. Moshopoulos (IOLTS, 2008)

An instruction set extension for java bytecodes translation acceleration. - Isidoros Sideris; Kiamal Z. Pekmestzi; George Economakos (ICSAMOS, 2008)

A predecoding technique for ILP exploitation in Java processors. - Isidoros Sideris; Kiamal Z. Pekmestzi; George Economakos (J. Syst. Archit., 2008)

Flexible Datapath Synthesis through Arithmetically Optimized Operation Chaining. - Sotirios Xydis; Ioannis Triantafyllou; George Economakos; Kiamal Z. Pekmestzi (AHS, 2009)

A design methodology for high-performance and low-leakage fixed-point transpose FIR filters. - Dimitris Bekiaris; Sotirios Xydis; George Economakos; Kiamal Z. Pekmestzi (ICECS, 2009)

Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths. - Sotirios Xydis; George Economakos; Kiamal Z. Pekmestzi (Integr., 2009)

Extending an embedded RISC microprocessor for efficient translation based Java execution. - Isidoros Sideris; Kiamal Z. Pekmestzi; George Economakos (Microprocess. Microsystems, 2009)

A bit level area aware cache-based architecture for memory repairs. - Nicholas Axelos; Kiamal Z. Pekmestzi (IOLTS, 2010)

Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology. - Sotirios Xydis; Christos Skouroumounis; Kiamal Z. Pekmestzi; Dimitrios Soudris; George Economakos (ISCAS, 2010)

A New Low-Power Soft-Error Tolerant SRAM Cell. - Nicholas Axelos; Kiamal Z. Pekmestzi; Nikolaos Moschopoulos (ISVLSI, 2010)

High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures. - Sotirios Xydis; Kiamal Z. Pekmestzi; Dimitrios Soudris; George Economakos (ISVLSI, 2010)

A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning. - Sotirios Xydis; Kiamal Z. Pekmestzi; Dimitrios Soudris; George Economakos (ISVLSI (Selected papers), 2010)

Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching. - Sotirios Xydis; Christos Skouroumounis; Kiamal Z. Pekmestzi; Dimitrios Soudris; George Economakos (ISVLSI, 2010)

A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework. - Dimitris Bekiaris; Antonis Papanikolaou; Christos Papameletis; Dimitrios Soudris; George Economakos; Kiamal Z. Pekmestzi (PATMOS, 2010)

A fast multiplier-less edge detection accelerator for FPGAs. - Nikos Anastasiadis; Isidoros Sideris; Kiamal Z. Pekmestzi (SAC, 2010)

A hardware peripheral for Java bytecodes translation acceleration. - Isidoros Sideris; Nikos K. Moshopoulos; Kiamal Z. Pekmestzi (SAC, 2010)

Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms. - Sotirios Xydis; Alexandros Bartzas; Iraklis Anagnostopoulos; Dimitrios Soudris; Kiamal Z. Pekmestzi (ICSAMOS, 2010)

On the Design of Modulo 2^n+1 Multipliers. - Constantinos Efstathiou; Kiamal Z. Pekmestzi; Nicholas Axelos (DSD, 2011)

High Performance and Area Efficient Flexible DSP Datapath Synthesis. - Sotirios Xydis; George Economakos; Dimitrios Soudris; Kiamal Z. Pekmestzi (IEEE Trans. Very Large Scale Integr. Syst., 2011)

On the Design of Configurable Modulo 2n±1 Residue Generators. - Constantinos Efstathiou; Nikolaos Moschopoulos; Kostas Tsoumanis; Kiamal Z. Pekmestzi (DSD, 2012)

Cost Effective Protection Techniques for TCAM Memory Arrays. - Isidoros Sideris; Kiamal Z. Pekmestzi (IEEE Trans. Computers, 2012)

Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs. - Sotirios Xydis; Kiamal Z. Pekmestzi; Dimitrios Soudris; George Economakos (ACM Trans. Design Autom. Electr. Syst., 2012)

Efficient Memory Repair Using Cache-Based Redundancy. - Nicholas Axelos; Kiamal Z. Pekmestzi; Dimitris Gizopoulos (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Efficient modulo 2n+1 multiplication for the idea block cipher. - Kiamal Z. Pekmestzi; Constantinos Efstathiou; Nikolaos Moschopoulos; Kostas Tsoumanis (ACM Great Lakes Symposium on VLSI, 2013)

A radiation tolerant and self-repair memory cell. - Nikolaos Eftaxiopoulos-Sarris; Georgios Zervakis 001; Kostas Tsoumanis; Kiamal Z. Pekmestzi (IOLTS, 2013)

On the design of modulo 2n±1 residue generators. - Kostas Tsoumanis; Constantinos Efstathiou; Nikolaos Moschopoulos; Kiamal Z. Pekmestzi (VLSI-SoC, 2013)

On the design of modulo 2n + 1 dot product and generalized multiply-add units. - Costas Efstathiou; Nikolaos Moschopoulos; Ioannis Voyiatzis; Kiamal Z. Pekmestzi (Comput. Electr. Eng., 2013)

A column parity based fault detection mechanism for FIFO buffers. - Isidoros Sideris; Kiamal Z. Pekmestzi (Integr., 2013)

A segmentation-based BISR scheme. - Georgios Zervakis 001; Nikolaos Eftaxiopoulos-Sarris; Kostas Tsoumanis; Nicholas Axelos; Kiamal Z. Pekmestzi (ASP-DAC, 2014)

On the design of efficient modulo 2n+1 multiply-add-add units. - Constantinos Efstathiou; Kostas Tsoumanis; Kiamal Z. Pekmestzi; Ioannis Voyiatzis (DTIS, 2014)

Fused modulo 2n - 1 add-multiply unit. - Kostas Tsoumanis; Kiamal Z. Pekmestzi; Constantinos Efstathiou (ICECS, 2014)

High performance MAC designs. - Nikolaos Eftaxiopoulos-Sarris; Georgios Zervakis 001; Kiamal Z. Pekmestzi; Costas Efstathiou (IDT, 2014)

An independent dual gate SOI FinFET soft-error resilient memory cell. - Nikolaos Eftaxiopoulos-Sarris; Nicholas Axelos; Georgios Zervakis 001; Kostas Tsoumanis; Kiamal Z. Pekmestzi (IDT, 2014)

Modulo 2n+1 addition and multiplication for redundant operands. - Kostas Tsoumanis; Constantinos Efstathiou; Kiamal Z. Pekmestzi (IDT, 2014)

A high radix montgomery multiplier with concurrent error detection. - Georgios Zervakis 001; Nikolaos Eftaxiopoulos-Sarris; Kostas Tsoumanis; Nicholas Axelos; Kiamal Z. Pekmestzi (IDT, 2014)

FF-DICE: An 8T soft-error tolerant cell using Independent Dual Gate SOI FinFETs. - Nicholas Axelos; Nikolaos Eftaxiopoulos-Sarris; Georgios Zervakis 001; Kostas Tsoumanis; Kiamal Z. Pekmestzi (IOLTS, 2014)

Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding. - Constantinos Efstathiou; Nikos K. Moshopoulos; Nicholas Axelos; Kiamal Z. Pekmestzi (Integr., 2014)

An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator. - Kostas Tsoumanis; Sotirios Xydis; Constantinos Efstathiou; Nikolaos Moschopoulos; Kiamal Z. Pekmestzi (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Approximate Multiplier Architectures Through Partial Product Perforation: Power-Area Tradeoffs Analysis. - Georgios Zervakis 001; Kostas Tsoumanis; Sotirios Xydis; Nicholas Axelos; Kiamal Z. Pekmestzi (ACM Great Lakes Symposium on VLSI, 2015)

Low leakage radiation tolerant CAM/TCAM cell. - Nikolaos Eftaxiopoulos-Sarris; Nicholas Axelos; Kiamal Z. Pekmestzi (IOLTS, 2015)

Hybrid approximate multiplier architectures for improved power-accuracy trade-offs. - Georgios Zervakis 001; Sotirios Xydis; Kostas Tsoumanis; Dimitrios Soudris; Kiamal Z. Pekmestzi (ISLPED, 2015)

Modulo 2n ± 1 Fused Add-Multiply Units. - Constantinos Efstathiou; Kostas Tsoumanis; Kiamal Z. Pekmestzi; Ioannis Voyiatzis (ISVLSI, 2015)

DONUT: A Double Node Upset Tolerant Latch. - Nikolaos Eftaxiopoulos; Nicholas Axelos; Kiamal Z. Pekmestzi (ISVLSI, 2015)

Delta DICE: A Double Node Upset resilient latch. - Nikolaos Eftaxiopoulos; Nicholas Axelos; Georgios Zervakis 001; Kostas Tsoumanis; Kiamal Z. Pekmestzi (MWSCAS, 2015)

Design of Efficient 1's Complement Modified Booth Multiplier. - Kiamal Z. Pekmestzi; Constantinos Efstathiou (DSD, 2016)

Fused modulo 2n + 1 add-multiply unit for weighted operands. - Kiamal Z. Pekmestzi; Kostas Tsoumanis; Constantinos Efstathiou (DTIS, 2016)

Low latency radiation tolerant self-repair reconfigurable SRAM architecture. - Nikolaos Eftaxiopoulos; Nicholas Axelos; Kiamal Z. Pekmestzi (Microelectron. Reliab., 2016)

Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding. - Kostas Tsoumanis; Nicholas Axelos; Nikolaos Moschopoulos; Georgios Zervakis 001; Kiamal Z. Pekmestzi (IEEE Trans. Computers, 2016)

Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic. - Kostas Tsoumanis; Sotirios Xydis; Georgios Zervakis 001; Kiamal Z. Pekmestzi (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation. - Georgios Zervakis 001; Kostas Tsoumanis; Sotirios Xydis; Dimitrios Soudris; Kiamal Z. Pekmestzi (IEEE Trans. Very Large Scale Integr. Syst., 2016)

On the design of the FFT Butterfly Units. - Fotis Douskas; Kiamal Z. Pekmestzi (MOCAST, 2017)

DIRT latch: A novel low cost double node upset tolerant latch. - Nikolaos Eftaxiopoulos; Nicholas Axelos; Kiamal Z. Pekmestzi (Microelectron. Reliab., 2017)

Efficient support vector machines implementation on Intel/Movidius Myriad 2. - Charalampos Marantos; Nikolaos Karavalakis; Vasileios Leon; Vasileios Tsoutsouras; Kiamal Z. Pekmestzi; Dimitrios Soudris (MOCAST, 2018)

Walking through the Energy-Error Pareto Frontier of Approximate Multipliers. - Vasileios Leon; Georgios Zervakis 001; Sotirios Xydis; Dimitrios Soudris; Kiamal Z. Pekmestzi (IEEE Micro, 2018)

Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers. - Vasileios Leon; Georgios Zervakis 001; Dimitrios Soudris; Kiamal Z. Pekmestzi (IEEE Trans. Very Large Scale Integr. Syst., 2018)

VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits. - Georgios Zervakis 001; Fotios Ntouskas; Sotirios Xydis; Dimitrios Soudris; Kiamal Z. Pekmestzi (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers. - Vasileios Leon; Konstantinos Asimakopoulos; Sotirios Xydis; Dimitrios Soudris; Kiamal Z. Pekmestzi (DAC, 2019)

TF2FPGA: A Framework for Projecting and Accelerating Tensorflow CNNs on FPGA Platforms. - Spyridon Mouselinos; Vasileios Leon; Sotirios Xydis; Dimitrios Soudris; Kiamal Z. Pekmestzi (MOCAST, 2019)

Energy-efficient VLSI implementation of multipliers with double LSB operands. - Vasileios Leon; Sotirios Xydis; Dimitrios Soudris; Kiamal Z. Pekmestzi (IET Circuits Devices Syst., 2019)

Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints. - Georgios Zervakis 001; Sotirios Xydis; Dimitrios Soudris; Kiamal Z. Pekmestzi (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Combining Arithmetic Approximation Techniques for Improved CNN Circuit Design. - George Lentaris; George Chatzitsompanis; Vasileios Leon; Kiamal Z. Pekmestzi; Dimitrios Soudris (ICECS, 2020)

Efficient design of magnitude and 2's complement comparators. - Fotios Ntouskas; Constantinos Efstathiou; Kiamal Z. Pekmestzi (Integr., 2020)

On the Diminished-1 Modulo 2n+1 Addition and Subtraction. - Constantinos Efstathiou; Kiamal Z. Pekmestzi; Nikolaos Moschopoulos (J. Circuits Syst. Comput., 2020)

Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators. - Vasileios Leon; Kiamal Z. Pekmestzi; Dimitrios Soudris (FPL, 2021)

Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers. - Vasileios Leon; Theodora Paparouni; Evangelos Petrongonas; Dimitrios Soudris; Kiamal Z. Pekmestzi (ACM Trans. Embed. Comput. Syst., 2021)

MAx-DNN: Multi-Level Arithmetic Approximation for Energy-Efficient DNN Hardware Accelerators. - Vasileios Leon; Georgios Makris; Sotirios Xydis; Kiamal Z. Pekmestzi; Dimitrios Soudris (LASCAS, 2022)

Systematic Embedded Development and Implementation Techniques on Intel Myriad VPUs. - Vasileios Leon; Kiamal Z. Pekmestzi; Dimitrios Soudris (VLSI-SoC, 2022)

Approximate Computing Survey, Part II: Application-Specific & Architectural Approximation Techniques and Applications. - Vasileios Leon; Muhammad Abdullah Hanif; Giorgos Armeniakos; Xun Jiao; Muhammad Shafique 001; Kiamal Z. Pekmestzi; Dimitrios Soudris (ACM Comput. Surv., 2025)

Approximate Computing Survey, Part I: Terminology and Software & Hardware Approximation Techniques. - Vasileios Leon; Muhammad Abdullah Hanif; Giorgos Armeniakos; Xun Jiao; Muhammed Shafique 001; Kiamal Z. Pekmestzi; Dimitrios Soudris (ACM Comput. Surv., 2025)