A low power delayed-clocks generation and distribution system. - Su Kio; Kian Haur Chong; Carl Sechen (ISCAS (5), 2003)

409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS. - Sheng Sun; Yi Han; Xinyu Guo; Kian Haur Chong; Larry McMurchie; Carl Sechen (ISVLSI, 2005)

A 64b adder using self-calibrating differential output prediction logic. - Kian Haur Chong; Larry McMurchie; Carl Sechen (ISSCC, 2006)