A Method for Noise Reduction in Active-RC Circuits. - Kiarash Gharibdoust; Mehrdad Sharif Bakhtiar (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (ISSCC, 2015)

A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (VLSIC, 2015)

Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE J. Solid State Circuits, 2015)

A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces. - Kiarash Gharibdoust; Gain Kim; Armin Tajalli; Yusuf Leblebici (ISCAS, 2016)

A wideband MDLL with jitter reduction scheme for forwarded clock serial links in 40 nm CMOS. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (NEWCAS, 2016)

A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE J. Solid State Circuits, 2016)

Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs. - Giulia Beanato; Kiarash Gharibdoust; Alessandro Cevrero; Giovanni De Micheli; Yusuf Leblebici (Microelectron. J., 2016)

A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces. - Gain Kim; Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme. - Gain Kim; Thierry Barailler; Chen Cao; Kiarash Gharibdoust; Yusuf Leblebici (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links. - Gain Kim; Chen Cao; Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET. - Armin Tajalli; Mani Bastani Parizi; Dario Albino Carnelli; Chen Cao; John Fox; Kiarash Gharibdoust; Davide Gorret; Amit Gupta; Christopher Hall; Ahmed Hassanin; Klaas L. Hofstra; Brian Holden; et al. (VLSI Circuits, 2019)

Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ. - Armin Tajalli; Mani Bastani Parizi; Dario Albino Carnelli; Chen Cao; Kiarash Gharibdoust; Amit Gupta; Ahmed Hassanin; Klaas L. Hofstra; Brian Holden; Ali Hormati; John Keay; Amin Shokrollahi; et al. (CICC, 2020)

A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET. - Armin Tajalli; Mani Bastani Parizi; Dario Albino Carnelli; Chen Cao; Kiarash Gharibdoust; Davide Gorret; Amit Gupta; Christopher Hall; Ahmed Hassanin; Klaas L. Hofstra; Brian Holden; Ali Hormati; et al. (IEEE J. Solid State Circuits, 2020)

An Orthogonal Pulse Amplitude Modulation Signaling for High-Speed Wireline Communications. - Fatemeh Akbar; Kiarash Gharibdoust (ISCAS, 2023)

A 16nm 140-fJ/b/dB Dual-Mode ENRZ/NRZ Serial Data Transceiver with Dynamic Voltage Scaling. - Armin Tajalli; Cosimo Aprile; Milad Ataei; Rolf Beerwerth; Dario Carneli; Maik Fuhs; Kiarash Gharibdoust; Ali Hormati; James Hudner; Victor Perrin; Amin Shokrollahi; Richard Simpson 004; et al. (CICC, 2025)