A charge-trapping-based technique to design low-voltage BiCMOS logic circuits. - Kiat Seng Yeo; Samir S. Rofail (IEEE J. Solid State Circuits, 1998)

A low-power 16×16-b parallel multiplier utilizing pass-transistor logic. - Chong-Fatt Law; Samir S. Rofail; Kiat Seng Yeo (IEEE J. Solid State Circuits, 1999)

An interconnect optimized floorplanning of a scalar product macrocell. - Jiangmin Gu; Chip-Hong Chang; Kiat Seng Yeo (ISCAS (1), 2002)

A 52 GHz VCO with Low Phase Noise Implemented in SiGe BiCMOS Technology. - Lin Jia; Alper Cabuk; Jianguo Ma; Kiat Seng Yeo (IWSOC, 2003)

Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling. - Beng Hwee Ong; Choon Beng Sia; Kiat Seng Yeo; Jianguo Ma; Manh Anh Do; Erping Li 001 (SLIP, 2004)

RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor. - Chirn Chye Boon; Manh Anh Do; Kiat Seng Yeo; Jianguo Ma; Xiaoling Zhang 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

A novel methodology for the design of LC tank VCO with low phase noise. - Lin Jia; Jianguo Ma; Kiat Seng Yeo; Manh Anh Do (ISCAS (1), 2005)

A 5GHz to 6GHz integrated differential LNA. - Wei Meng Lim; Han Guo Ma; Manh Anh Do; Kiat Seng Yeo (ISCAS (5), 2005)

A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration. - Myint Wai Phyu; Wang Ling Goh; Kiat Seng Yeo (ISCAS (3), 2005)

A new 5 GHz CMOS dual-modulus prescaler. - Xiaopeng Yu 002; Manh Anh Do; Jianguo Ma; Kiat Seng Yeo (ISCAS (5), 2005)

An Ultra Low-power Current-mode Sense Amplifier for Sram Applications. - Zhi-Hui Kong; Kiat Seng Yeo; Chip-Hong Chang (J. Circuits Syst. Comput., 2005)

Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction. - Chirn Chye Boon; Manh Anh Do; Kiat Seng Yeo; Jianguo Ma (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A modified architecture used for input matching in CMOS low-noise amplifiers. - Shouxian Mou; Jianguo Ma; Kiat Seng Yeo; Manh Anh Do (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Equivalent circuit model of on-wafer CMOS interconnects for RFICs. - Xiaomeng Shi; Jianguo Ma; Kiat Seng Yeo; Manh Anh Do; Erping Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Design of a low power wide-band high resolution programmable frequency divider. - Xiaopeng Yu 002; Manh Anh Do; Lin Jia; Jianguo Ma; Kiat Seng Yeo (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs. - Shan Jiang; Manh Anh Do; Kiat Seng Yeo (VLSI-SoC, 2006)

A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs. - Shan Jiang; Manh Anh Do; Kiat Seng Yeo (VLSI-SoC (Selected Papers), 2006)

A New Phase Noise Model for TSPC based divider. - Xiaopeng Yu 002; Manh Anh Do; Jianguo Ma; Kiat Seng Yeo (VLSI-SoC, 2006)

Cmos Even Harmonic Switching mixer for Direct Conversion Receivers. - J. J. Liu; Manh Anh Do; Xiaopeng Yu 002; Kiat Seng Yeo; Shan Jiang; Jianguo Ma (J. Circuits Syst. Comput., 2006)

A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers. - Yang Lu; Kiat Seng Yeo; Alper Cabuk; Jianguo Ma; Manh Anh Do; Zhenghao Lu (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Distortion of pulsed signals in carbon nanotube interconnects. - Xiaomeng Shi; Kiat Seng Yeo; Jianguo Ma; Manh Anh Do (Microelectron. J., 2007)

Broad-Band Design Techniques for Transimpedance Amplifiers. - Zhenghao Lu; Kiat Seng Yeo; Jianguo Ma; Manh Anh Do; Wei Meng Lim; Xueying Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A full current-mode sense amplifier for low-power SRAM applications. - Anh-Tuan Do; Jeremy Yung Shern Low; Zhi-Hui Kong; Kiat Seng Yeo; Joshua Yung Low Yung Lih (APCCAS, 2008)

Body-bootstrapped-buffer circuit for CMOS static power reduction. - Liang-Yu Loy; Weija Zhang; Zhi-Hui Kong; Wang Ling Goh; Kiat Seng Yeo (APCCAS, 2008)

Spicesoft: Automated Tool for Sensitivity Analysis, Performance Analysis, and Inverse Performance Analysis of Digital Circuits. - Kiat Seng Yeo; Zhi-Hui Kong (J. Circuits Syst. Comput., 2008)

Integrated Circuit Design Research Ranking for Worldwide Universities. - Kiat Seng Yeo; Zhi-Hui Kong; Nukala Nishant; Haitao Fu; Wei Zeng (J. Circuits Syst. Comput., 2008)

Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing. - Anh-Tuan Do; Zhi-Hui Kong; Kiat Seng Yeo (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit. - Shan Jiang; Manh Anh Do; Kiat Seng Yeo; Wei Meng Lim (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs. - Xiaomeng Shi; Kiat Seng Yeo; Jianguo Ma; Manh Anh Do; Erping Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Low IR drop and low power parallel CAM design using gated power transistor technique. - Anh-Tuan Do; Shoushun Chen; Zhi-Hui Kong; Kiat Seng Yeo (APCCAS, 2010)

An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving. - Anh-Tuan Do; Kiat Seng Yeo; Jeremy Yung Shern Low; Joshua Yung Lih Low; Zhi-Hui Kong (APCCAS, 2010)

Low power millimeter wave active sige sub-harmonic up-conversion mixer with ultra low driving power. - Kok Meng Lim; Jiangmin Gu; Yang Lu; Jinna Yan; Wei Meng Lim; Kaixue Ma; Kiat Seng Yeo (ICECS, 2010)

A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output pole. - Aaron V. T. Do; Chirn Chye Boon; Manh Anh Do; Kiat Seng Yeo; Alper Cabuk (VLSI-SoC, 2010)

A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole. - Aaron V. T. Do; Chirn Chye Boon; Manthena Vamshi Krishna; Manh Anh Do; Kiat Seng Yeo (VLSI-SoC (Selected Papers), 2010)

A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4. - Manthena Vamshi Krishna; Xuan Jie; Manh Anh Do; Chirn Chye Boon; Kiat Seng Yeo; Aaron V. T. Do (VLSI-SoC (Selected Papers), 2010)

A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4. - Manthena Vamshi Krishna; Juan Xie; Manh Anh Do; Chirn Chye Boon; Kiat Seng Yeo; Aaron V. T. Do (VLSI-SoC, 2010)

An Energy-Aware CMOS Receiver Front End for Low-Power 2.4-GHz Applications. - Aaron V. T. Do; Chirn Chye Boon; Manh Anh Do; Kiat Seng Yeo; Alper Cabuk (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier. - Anh-Tuan Do; Zhi-Hui Kong; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler. - Manthena Vamshi Krishna; Manh Anh Do; Kiat Seng Yeo; Chirn Chye Boon; Wei Meng Lim (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A Wideband Low Power Low-Noise Amplifier in CMOS Technology. - Ali Meaamar; Chirn Chye Boon; Kiat Seng Yeo; Manh Anh Do (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback. - Zhenghao Lu; Kiat Seng Yeo; Wei Meng Lim; Manh Anh Do; Chirn Chye Boon (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing. - Ning Zhu; Wang Ling Goh; Weija Zhang; Kiat Seng Yeo; Zhi-Hui Kong (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter. - Deyun Cai; Haipeng Fu; Junyan Ren; Wei Li 038; Ning Li 007; Hao Yu 001; Kiat Seng Yeo (A-SSCC, 2011)

A new match line sensing technique in Content Addressable Memory. - Xiaoliang Tan; Anh-Tuan Do; Shoushun Chen; Kiat Seng Yeo; Zhi-Hui Kong (COOL Chips, 2011)

A comparative study of state-of-the-art low-power CAM match-line sense amplifier designs. - Anh-Tuan Do; Xiaoliang Tan; Shoushun Chen; Zhi-Hui Kong; Kiat Seng Yeo (ACM Great Lakes Symposium on VLSI, 2011)

A low-power CAM with efficient power and delay trade-off. - Anh-Tuan Do; Shoushun Chen; Zhi-Hui Kong; Kiat Seng Yeo (ISCAS, 2011)

A 3.1-8 GHz CMOS UWB front-end receiver. - Ali Meaamar; Chirn Chye Boon; Xiaomeng Shi; Wei Meng Lim; Kiat Seng Yeo; Manh Anh Do (ISCAS, 2011)

Ultra low power active 60 GHz Bi-CMOS down-conversion mixer. - Kok Meng Lim; Jiangmin Gu; Jinna Yan; Wei Meng Lim; Yang Lu; Kiat Seng Yeo (ISOCC, 2011)

A 60GHz BiCMOS self-demodulator with injection locked oscillator. - Zhenghao Lu; Xiaopeng Yu 002; Kiat Seng Yeo; Wei Meng Lim; Jinna Yan; Renjing Pan (ISOCC, 2011)

A 60GHz defected ground power divider using SiGe BiCMOS technology. - Kaixue Ma; Shouxian Mou; Yang Lu; Kok Meng Lim; Kiat Seng Yeo (ISOCC, 2011)

Wide center-tape balun for 60 GHz silicon RF ICs. - Fanyi Meng; Kiat Seng Yeo; Shanshan Xu; Kaixue Ma; Chee Chong Lim (ISOCC, 2011)

SiGe BiCMOS power amplifiers for 60GHz ISM band applications. - Renjing Pan; Jiangmin Gu; Kiat Seng Yeo; Wei Meng Lim; Kaixue Ma (ISOCC, 2011)

A DC to 14GHz fully differential amplifier for wideband low power applications. - Bharatha Kumar Thangarasu; Kaixue Ma; Kiat Seng Yeo; Shouxian Mou; Mahalingam Nagarajan (ISOCC, 2011)

Design consideration for 60 GHz SiGe power amplifier with ESD protection. - Keping Wang; Kaixue Ma; Kiat Seng Yeo (ISOCC, 2011)

A double-quadrature down-conversion mixer in 0.18 μm SiGe BiCMOS process. - Jinna Yan; Kok Meng Lim; Jiangmin Gu; Keping Wang; Wei Meng Lim; Kaixue Ma; Kiat Seng Yeo (ISOCC, 2011)

Ultra low-power high-speed flexible Probabilistic Adder for Error-Tolerant Applications. - Ning Zhu; Wang Ling Goh; Kiat Seng Yeo (ISOCC, 2011)

A low power wide tuning range VCO with coupled LC tanks. - Shouxian Mou; Kaixue Ma; Kiat Seng Yeo; Nagarajan Mahalingam; Bharatha Kumar Thangarasu (SoCC, 2011)

Adaptive priority toggle asynchronous tree arbiter for AER-based image sensor. - Myat Thu Linn Aung; Anh-Tuan Do; Shoushun Chen; Kiat Seng Yeo (VLSI-SoC, 2011)

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS. - Anh-Tuan Do; Jeremy Yung Shern Low; Joshua Yung Lih Low; Zhi-Hui Kong; Xiaoliang Tan; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A Low-Loss Image-Reject Mixer Using Source Follower Isolation Method for DRM/DAB Tuner Applications. - Keping Wang; Zhigong Wang; Xuemei Lei; Xiang Cao; Peng Han; Geliang Yang; Kaixue Ma; Kiat Seng Yeo (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM. - Anh-Tuan Do; Zhi-Hui Kong; Kiat Seng Yeo; Jeremy Yung Shern Low (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops. - Myint Wai Phyu; Kangkang Fu; Wang Ling Goh; Kiat Seng Yeo (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A 12-GHz high output power amplifier using 0.18µm SiGe BiCMOS for low power applications. - Bharatha Kumar Thangarasu; Kaixue Ma; Kiat Seng Yeo; Wei Meng Lim (APCCAS, 2012)

A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems. - Anh-Tuan Do; Chun Kit Lam; Yung Sern Tan; Kiat Seng Yeo; Jia Hao Cheong; Lei Yao; Meng Tong Tan; Minkyu Je (APCCAS, 2012)

Recent progress in silicon-based millimeter-wave power amplifier. - Jiang An Han; Zhi-Hui Kong; Kaixue Ma; Kiat Seng Yeo (APCCAS, 2012)

On-chip tunable low pass filter with improved stopband using new cross coupled topology. - Kaixue Ma; Shouxian Mou; Kiat Seng Yeo; Wei Meng Lim (APCCAS, 2012)

Design of quarter-wavelength resonator filters with coupling controllable paths. - Fanyi Meng; Kaixue Ma; Shanshan Xu; Kiat Seng Yeo; Chirn Chye Boon; Wei Meng Lim; Manh Anh Do (APCCAS, 2012)

A 96×96 1V ultra-low power CMOS image sensor for biomedical application. - Tongxi Wang; Xiwei Huang; Mei Yan; Hao Yu 001; Kiat Seng Yeo; Ismail Cevik; Suat U. Ay (APCCAS, 2012)

Low-power high-speed dual-modulus prescaler for Gb/s applications. - Keping Wang; Kaixue Ma; Kiat Seng Yeo (APCCAS, 2012)

A 60GHz on-chip antenna in standard CMOS silicon Technology. - Wanlan Yang; Kaixue Ma; Kiat Seng Yeo; Wei Meng Lim (APCCAS, 2012)

Integrated circuits design for neural recording sensor interface. - Xiaodan Zou; Lei Liu; Yung Sern Tan; Minkyu Je; Kiat Seng Yeo (APCCAS, 2012)

A low power millimetre-wave VCO in 0.18 µm SiGe BiCMOS technology. - Qiong Zou; Kaixue Ma; Wanxin Ye; Kiat Seng Yeo (APCCAS, 2012)

A super-resolution CMOS image sensor for bio-microfluidic imaging. - Tongxi Wang; Xiwei Huang; Qixiang Jia; Mei Yan; Hao Yu 001; Kiat Seng Yeo (BioCAS, 2012)

High-speed CMOS image sensor for high-throughput lensless microfluidic imaging system. - Mei Yan; Xiwei Huang; Qixiang Jia; Revanth Nadipalli; Tongxi Wang; Yang Shang; Hao Yu 001; Minkyu Je; Kiat Seng Yeo (Sensors, Cameras, and Systems for Industrial and Scientific Applications, 2012)

Designs of a free-space white-LED mass-storage transceiver for SD-card file transfer. - Lih Chieh Png; Nhat Le Minh; Liangquan Chen; Kiat Seng Yeo (GLOBECOM Workshops, 2012)

An optimum RF link for implantable devices with rectification of transmission errors. - Zhong Qiang Ding; Kiat Seng Yeo (ISOCC, 2012)

Low power implantable neural recording front-end. - Anh-Tuan Do; Yung Sern Tan; Chun Kit Lam; Minkyu Je; Kiat Seng Yeo (ISOCC, 2012)

A 57∼66GHz CMOS voltage-controlled oscillator using tunable differential inductor. - Haitao Wang; Kiat Seng Yeo; Anh-Tuan Do; Yung Sern Tan; Kai Kang; Zhenghao Lu (ISOCC, 2012)

A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications. - Anh-Tuan Do; Chun Kit Lam; Yung Sern Tan; Kiat Seng Yeo; Jia Hao Cheong; Xiaodan Zou; Lei Yao; Kuang-Wei Cheng; Minkyu Je (NEWCAS, 2012)

Foreword. - Pak Kwong Chan; Chip-Hong Chang; Kiat Seng Yeo (J. Circuits Syst. Comput., 2012)

A robust 900 MHz RFID Reader Chip with RC-Calibration. - Shouxian Mou; Kaixue Ma; Kiat Seng Yeo (J. Circuits Syst. Comput., 2012)

A low power low phase noise dual-band multiphase VCO. - Juan Xie; Manthena Vamshi Krishna; Manh Anh Do; Chirn Chye Boon; Kiat Seng Yeo (Microelectron. J., 2012)

Sensing Margin Enhancement Techniques for Ultra-Low-Voltage SRAMs Utilizing a Bitline-Boosting Current and Equalized Bitline Leakage. - Anh-Tuan Do; Truc Quynh Nguyen; Kiat Seng Yeo; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector. - Yung Sern Tan; Kiat Seng Yeo; Chirn Chye Boon; Manh Anh Do (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Design of a Ku-band Low-Phase-Noise VCO Using the Dual LC Tanks. - Qiong Zou; Kaixue Ma; Kiat Seng Yeo; Wei Meng Lim (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis. - Wei Fei; Hao Yu 001; Wei Zhang 012; Kiat Seng Yeo (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A Low-Power Single-Phase Clock Multiband Flexible Divider. - Manthena Vamshi Krishna; Manh Anh Do; Chirn Chye Boon; Kiat Seng Yeo (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A 24 GHz reconfigurable frequency synthesizer for 60 GHz WPAN. - Nagarajan Mahalingam; Yisheng Wang; Kaixue Ma; Shouxian Mou; Kiat Seng Yeo (ASICON, 2013)

Design of a power-efficient CAM using automated background checking scheme for small match line swing. - Anh Tuan Do; Chun Yin; Kiat Seng Yeo; Tony Tae-Hyoung Kim (ESSCIRC, 2013)

Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset. - Anh-Tuan Do; Karthik G. Jayaraman; Pushpapraj Singh; Chua Geng Li; Kiat Seng Yeo; Tony Tae-Hyoung Kim (ESSDERC, 2013)

An improved read/write scheme for anchorless NEMS-CMOS non-volatile memory. - Anh-Tuan Do; Karthik G. Jayaraman; Vincent Pott; Chua Geng Li; Pushpapraj Singh; Kiat Seng Yeo; Tony Tae-Hyoung Kim (ISCAS, 2013)

A current-mode stimulator circuit with two-step charge balancing background calibration. - Anh-Tuan Do; Yung Sern Tan; Gordon M. Xiong; Cleo Choong; Zhi-Hui Kong; Kiat Seng Yeo (ISCAS, 2013)

MIMO-diversity switching techniques for digital transmission in visible light communication. - Lih Chieh Png; Long Xiao; Kiat Seng Yeo; Thin Sek Wong; Yong Liang Guan 001 (ISCC, 2013)

Optical infrastructure for visible light communication for public housing and commercial buildings. - Lih Chieh Png; Kiat Seng Yeo (ISCC, 2013)

A low power wideband differential transimpedance amplifier for optical receivers in 0.18-μm CMOS. - Whye Seng Chong; Yung Sern Tan; Kiat Seng Yeo (NEWCAS, 2013)

A 12-mW 40-60-GHz 0.18- $ mu { hbox {m}}$ BiCMOS Oscillator-Less Self-Demodulator for Short-Range Software-Defined Transceivers. - Xiaopeng Yu 002; Zhenghao Lu; Bo Yu Hu; Wei Meng Lim; Er Tai Duo; Kiat Seng Yeo (IEEE J. Emerg. Sel. Topics Circuits Syst., 2013)

A Low Power Push-Push VCO using Multi-Coupled LC Tanks. - Mahalingam Nagarajan; Kaixue Ma; Kiat Seng Yeo; Wei Meng Lim (J. Circuits Syst. Comput., 2013)

A CMOS Low-Power temperature-robust RSSI using Weak-Inversion limiting amplifiers. - Keping Wang; Xuemei Lei; Kaixue Ma; Kiat Seng Yeo; Xiang Cao; Zhigong Wang (J. Circuits Syst. Comput., 2013)

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter. - Deyun Cai; Haipeng Fu; Junyan Ren; Wei Li 038; Ning Li 007; Hao Yu 001; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

K-band High-PAE Wide-Tuning-Range VCO Using Triple-Coupled LC Tanks. - Nagarajan Mahalingam; Kaixue Ma; Kiat Seng Yeo; Wei Meng Lim (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Cross-Coupled Current Conveyor Based CMOS Transimpedance Amplifier for Broadband Data Transmission. - Dandan Chen; Kiat Seng Yeo; Xiaomeng Shi; Manh Anh Do; Chirn Chye Boon; Wei Meng Lim (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing. - Anh-Tuan Do; Shoushun Chen; Zhi-Hui Kong; Kiat Seng Yeo (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A hybrid NEO-based spike detection algorithm for implantable brain-IC interface applications. - Anh-Tuan Do; Kiat Seng Yeo (ISCAS, 2014)

Internet of Things: Trends, challenges and applications. - Kiat Seng Yeo; Mojy Curtis Chian; Tony Chon Wee Ng; Anh-Tuan Do (ISIC, 2014)

A 64×64 1200fps CMOS ion-image sensor with suppressed fixed-pattern-noise for accurate high-throughput DNA sequencing. - Xiwei Huang; Fei Wang; Jing Guo; Mei Yan; Hao Yu 001; Kiat Seng Yeo (VLSIC, 2014)

Design and Analysis of a 2.4 GHz Hybrid Type Automatic amplitude Control VCO with Forward noise Reduction. - Y. X. Zhang; Chirn Chye Boon; Kiat Seng Yeo (J. Circuits Syst. Comput., 2014)

0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance. - Anh-Tuan Do; Chun Yin; Kavitha Velayudhan; Zhao Chuan Lee; Kiat Seng Yeo; Tony Tae-Hyoung Kim (IEEE J. Solid State Circuits, 2014)

Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer. - Wei Fei; Hao Yu 001; Haipeng Fu; Junyan Ren; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Analysis and Design of Ultra-Wideband Low-Noise Amplifier With Input/Output Bandwidth Optimization and Single-Ended/Differential-Input Reconfigurability. - Bo Yu Hu; Xiaopeng Yu 002; Wei Meng Lim; Kiat Seng Yeo (IEEE Trans. Ind. Electron., 2014)

A 57 to 66 GHz novel six-port correlator. - Peng Siew Chew; Kiat Seng Yeo; Kaixue Ma; Zhi-Hui Kong (ASICON, 2015)

A 32kb 9T SRAM with PVT-tracking read margin enhancement for ultra-low voltage operation. - Anh-Tuan Do; Kiat Seng Yeo; Tony Tae-Hyoung Kim (ISCAS, 2015)

Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits. - Seyed Mohammad Ali Zeinolabedin; Anh-Tuan Do; Kiat Seng Yeo; Tony Tae-Hyoung Kim (ISCAS, 2015)

2.3 A 130-to-180GHz 0.0035mm2 SPDT switch with 3.3dB loss and 23.7dB isolation in 65nm bulk CMOS. - Fanyi Meng; Kaixue Ma; Kiat Seng Yeo (ISSCC, 2015)

2.5 A 2-to-6GHz Class-AB power amplifier with 28.4% PAE in 65nm CMOS supporting 256QAM. - Wanxin Ye; Kaixue Ma; Kiat Seng Yeo (ISSCC, 2015)

A 65 nm CMOS Power Amplifier With Peak PAE above 18.9% From 57 to 66 GHz Using Synthesized Transformer-Based Matching Network. - Wanxin Ye; Kaixue Ma; Kiat Seng Yeo; Qiong Zou (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Low Phase Noise and Wide Tuning Range Millimeter-Wave VCO Using Switchable Coupled VCO-Cores. - Qiong Zou; Kaixue Ma; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An inductorless transimpedance amplifier design for 10 Gb/s optical communication using 0.18-µm CMOS. - Bai Song Samuel Lee; Yung Sern Tan; Bharatha Kumar Thangarasu; Kiat Seng Yeo; Zhichao Li; Xiaopeng Yu 002 (ISIC, 2016)

A 60-GHz power amplifier with efficiency enhancement at power back-off. - Zhichao Li; Bharatha Kumar Thangarasu; Xiaopeng Yu 002; Kiat Seng Yeo (ISIC, 2016)

A wideband digital variable gain amplifier with DC offset cancellation in SiGe 0.18µm BiCMOS technology. - Muting Lu; Bharatha Kumar Thangarasu; Dawei Zhang; Xiaopeng Yu 002; Kiat Seng Yeo (ISIC, 2016)

DC-50 GHz low loss switch matrix design in high resistivity trap-rich SOI. - Bo Yu; Kaixue Ma; Fanyi Meng; Bharatha Kumar Thangarasu; Kiat Seng Yeo (ISIC, 2016)

Design of millimeter-wave transformer balun with isolation circuit in silicon based technology. - Dawei Zhang; Hongxi Yu; Bharatha Kumar Thangarasu; Kai Men; Muting Lu; Xiaopeng Yu 002; Kiat Seng Yeo (ISIC, 2016)

Millimetre-wave performance of passive microstrip bandpass filters based on 40nm CMOS technology. - Xi Sung Loo; Kok Wai Johnny Chew; Michael Cheng; Kiat Seng Yeo (MWSCAS, 2016)

A 11.2 mW 48-62 GHz Low Noise Amplifier in 65 nm CMOS Technology. - Xiaopeng Yu 002; Wen Lin Xu; Chen Feng; Zhenghao Lu; Wei Meng Lim; Kiat Seng Yeo (Circuits Syst. Signal Process., 2016)

A 57-to-64-GHz 0.094-mm2 5-bit Passive Phase Shifter in 65-nm CMOS. - Fanyi Meng; Kaixue Ma; Kiat Seng Yeo; Shanshan Xu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

RF mixer design techniques using GaAs process. - Jinna Yan; Bharatha Kumar Thangarasu; Kiat Seng Yeo (ASICON, 2017)

Micro-LED arrays for display and communication: Device structure and driver architecture. - Kiat Seng Yeo; Wen Xian Ng; Mei Yu Soh; Tee Hui Teo (ASICON, 2017)

The Investigation and Optimisation of Phase-Induced Amplitude Attenuation in the Injection-Locked Ring Oscillators-Based Receiver. - Xiaopeng Yu 002; Zhe Liu 038; De Zhang Fan; Kiat Seng Yeo (Circuits Syst. Signal Process., 2017)

Evaluation of Low Voltage Rectifier Design Using IGBT, MOSFET, and GaN FETs. - Denise Lee; Mei Yu Soh; Tee Hui Teo; Kiat Seng Yeo (TENCON, 2018)

Precompliance Test Setup for Pyroelectric Sensor Devices in IoT Applications. - Denise Lee; Mei Yu Soh; Tee Hui Teo; Kiat Seng Yeo (TENCON, 2018)

Low-cost Real-time Video Streaming System Using Off-the-Shelf LEDs. - Mei Yu Soh; Wen Xian Ng; Qiong Zou; Denise Lee; Tee Hui Teo; Kiat Seng Yeo (TENCON, 2018)

Real-Time Audio Transmission Using Visible Light Communication. - Mei Yu Soh; Wen Xian Ng; Qiong Zou; Denise Lee; Tee Hui Teo; Kiat Seng Yeo (TENCON, 2018)

A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS. - Yun Fang; Xiaopeng Yu 002; Zheng Shi 002; Kiat Seng Yeo (Integr., 2018)

Design and optimization of the ring oscillator based injection locked frequency dividers. - Qi-Lin Qiu; Xiaopeng Yu 002; Wen-quan Sui; Kiat Seng Yeo (Microelectron. J., 2018)

An Inductorless 5-GHz Differential Dual Regulated Cross-Cascode Transimpedance Amplifier using 40 nm CMOS. - Bai Song Samuel Lee; Hang Liu 006; Xiaopeng Yu 002; Jer-Ming Chen; Kiat Seng Yeo (ASICON, 2019)

An Inductorless 6-GHz Variable Gain Differential Transimpedance Amplifier in 0.18-μm SiGe BiCMOS. - Bai Song Samuel Lee; Hang Liu 006; Kiat Seng Yeo (ISCAS, 2019)

A K-Band Differential SiGe Stacked Power Amplifier Based on Capacitive Compensation Techniques for Gain Enhancements. - Xi Sung Loo; Kiat Seng Yeo; Moe Z. Win; Zhichao Li; Xiaopeng Yu 002; Jer-Ming Chen (MWSCAS, 2019)

Millimeter-wave Sine Corrugated Fermi Tapered Slot Antenna Array Based on Partial Synthesized Dielectric. - Xi Sung Loo; Moe Z. Win; Kiat Seng Yeo; Wanlan Yang (RWS, 2019)

A Multi-Mode Multi-Coil Coupled Tuned Inductive Peaking ILFD for Low Injected Power With Compact Size. - Nagarajan Mahalingam; Kaixue Ma; Kiat Seng Yeo (IEEE Access, 2019)

A Wideband dB-Linear VGA With Temperature Compensation and Active Load. - Xiong Song; Zhenghao Lu; Liying Cai; Xiaopeng Yu 002; Kiat Seng Yeo; Jer-Ming Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Reliability-Oriented Startup Analysis of Injection-Locked Frequency Divider Based on Broken Symmetry Theory. - Yun Fang; Zhong Tang; Xiao-Peng Yu 002; Zheng Shi 002; Kiat Seng Yeo (IEEE Trans. Very Large Scale Integr. Syst., 2019)

An Ultra-Low Power 900 MHz Intermediate Frequency Low Noise Amplifier For Low-Power RF Receivers. - Aasish Boora; Bharatha Kumar Thangarasu; Kiat Seng Yeo (SoCC, 2020)

A data-dependent energy reduction algorithm for SAR ADC using self-adaptive window. - Haowei Lu 001; Xiao-Peng Yu 002; Zhenghao Lu; Kiat Seng Yeo; Jer-Ming Chen (Microelectron. J., 2020)

Design of a Wideband Variable-Gain Amplifier With Self-Compensated Transistor for Accurate dB-Linear Characteristic in 65 nm CMOS Technology. - Lingshan Kong; Hang Liu 006; Xi Zhu 001; Chirn Chye Boon; Chenyang Li 008; Zhe Liu 038; Kiat Seng Yeo (IEEE Trans. Circuits Syst., 2020)

A New Degeneration Technique for 60 GHz Triple Cascode Wideband Low Noise Amplifier. - Thurein Aung; Mahalingam Nagarajan; Kiat Seng Yeo (ASICON, 2021)

A Monolithically Integrated Single-Input Load-Modulated Balanced Amplifier With Enhanced Efficiency at Power Back-Off. - Lang Chen; Hang Liu 006; Jefferson A. Hora; J. Andrew Zhang; Kiat Seng Yeo; Xi Zhu 001 (IEEE J. Solid State Circuits, 2021)

A digital background calibration scheme for non-linearity of SAR ADC using back-propagation algorithm. - Haowei Lu 001; Xiao-Peng Yu 002; Si-Qi Wang; Yu-Yan Liu; Zhenyan Huang; Zhenghao Lu; Kiat Seng Yeo; Jer-Ming Chen (Microelectron. J., 2021)

A 60 GHz 8-Way Combined Power Amplifier in 0.18 μm SiGe BiCMOS. - Hang Liu 006; Xi Zhu 001; Yisheng Wang; Kai Men; Kiat Seng Yeo (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Decentralized and Lightweight Approach to Detect Eclipse Attacks on Proof of Work Blockchains. - Bithin Alangot; Daniël Reijsbergen; Sarad Venugopalan; Pawel Szalachowski; Kiat Seng Yeo (IEEE Trans. Netw. Serv. Manag., 2021)

Concurrent Multiband CMOS Low Noise Amplifier Design for Internet of Things Applications. - Peerapat Phetpadriew; Bharatha Kumar Thangarasu; Nagarajan Mahalingam; Zhenghao Lu; Cher Ming Tan; Kiat Seng Yeo (ASICON, 2023)

Distributed Anomaly Detection in Smart Grids: A Federated Learning-Based Approach. - J. Jithish; Bithin Alangot; Nagarajan Mahalingam; Kiat Seng Yeo (IEEE Access, 2023)

A Linear-in-Decibel Automatic Gain Control Amplifier With Dual Mode Continuous Gain Tuning. - Liying Cai; Xiong Song; Zhenghao Lu; Xiao-Peng Yu 002; Kiat Seng Yeo; Jer-Ming Chen; Bharatha Kumar Thangarasu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Towards Safe and Efficient Analog Circuit Design: Active Learning for Feasibility Region Exploration. - Sezin Kircali Ata; Zhi-Hui Kong; Anusha James; Lile Cai; Kiat Seng Yeo; Khin Mi Mi Aung; Chuan Sheng Foo; Ashish James (APCCAS, 2024)

The Initialization Factor: Understanding its Impact on Active Learning for Analog Circuit Design. - Sezin Kircali Ata; Zhi-Hui Kong; Anusha James; Lile Cai; Kiat Seng Yeo; Khin Mi Mi Aung; Chuan Sheng Foo; Ashish James (ISCAS, 2024)

A S/C-Band 5-Bit Passive Attenuator With Phase-Lead Compensation in 55-nm Bulk CMOS. - Genyin Ma; Fanyi Meng; Keping Wang; Kaixue Ma; Kiat Seng Yeo (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 211.4-to-234.8 GHz 25.6-dB Differential Amplifier With Compact Terminal Multi-Coupled and Auxiliary Interstage-Coupled Matching Networks. - Zenglong Zhao; Xianghui Chen; Fanyi Meng; Kaixue Ma; Kiat Seng Yeo (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 28/39 GHz Tri-Mode Frequency-Reconfigurable LNA for Multiband 5G Communications. - Bing Liu; Fanyi Meng; Zonglin Ma; Kiat Seng Yeo; Kaixue Ma (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Evolution of and Perspectives on Differential-Pair-Based CMOS Variable Gain Amplifiers With Linear-in-Decibel Gain Control: A Tutorial. - Siqi Wang; Zhenghao Lu; Zhong Tang; Xiaopeng Yu 002; Hanming Wu; Kiat Seng Yeo; Yong Chen 005 (Int. J. Circuit Theory Appl., 2025)

Federated learning for sustainable intrusion detection systems: A review of green computing strategies and future directions. - J. Jithish; Nagarajan Mahalingam; Bo Wang 020; Kiat Seng Yeo (Internet Things, 2025)

A dB-Linear Programmable Gain Amplifier With Mixed-Signal Control for Wide-Gain Range and Low-Power Applications. - Aasish Boora; Bharatha Kumar Thangarasu; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Design and Analysis of a 22.6-to-73.9 GHz Low-Noise Amplifier for 5G NR FR2 and NR-U Multiband/Multistandard Communications. - Zenglong Zhao; Xianghui Chen; Fanyi Meng; Zhen Yang 017; Bing Liu; Nengxu Zhu; Keping Wang; Kaixue Ma; Kiat Seng Yeo (IEEE J. Solid State Circuits, 2025)

Towards enhancing security for upcoming 6G-ready smart grids through federated learning and cloud solutions. - J. Jithish; Nagarajan Mahalingam; Bo Wang 020; Kiat Seng Yeo (Cybersecur., 2025)