A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. - Kibong Koo; Sunghwa Ok; Yonggu Kang; Seungbong Kim; Choungki Song; Hyeyoung Lee; Hyungsoo Kim; Yongmi Kim; Jeonghun Lee; Seunghan Oak; Yosep Lee; Jungyu Lee 002; et al. (ISSCC, 2012)

A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme. - Dongkyun Kim; Minsu Park; Sungchun Jang; Jun-Yong Song; Hankyu Chi; Geunho Choi; Sunmyung Choi; Jaeil Kim; Changhyun Kim; Kyung Whan Kim; Kibong Koo; Seonghwi Song; et al. (ISSCC, 2019)

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx. - Dongkyun Kim; Kibong Koo; Yongmi Kim; Dong-Uk Lee; Jaejin Lee; Ki Hun Kwon; Byeongchan Choi; Hongjung Kim; Sanghyun Ku; Jong-Sam Kim; Seungwook Oh; Minsu Park; et al. (IEEE J. Solid State Circuits, 2020)