Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor. - Hisashige Ando; Ryuji Kan; Yoshiharu Tosaka; Keiji Takahisa; Kichiji Hatanaka (DSN, 2008)

Investigation of multi cell upset in sequential logic and validity of redundancy technique. - Taiki Uemura; Takashi Kato; Hideya Matsuyama; Keiji Takahisa; Mitsuhiro Fukuda; Kichiji Hatanaka (IOLTS, 2011)