Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation. - Dipjyoti Das; Lance Fernandes; Prasanna Venkatesan Ravindran; Taeyoung Song; Chinsung Park; Nashrah Afroze; Mengkun Tian; Hang Chen; Winston Chem; Kijoon Kim; Jongho Woo; Suhwan Lim; et al. (IMW, 2024)

Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET. - Taeyoung Kim; Suhwan Lim; Ilho Myeong; Sanghyun Park; Suseong Noh; Seung Min Lee; Jongho Woo; Hanseung Ko; Youngji Noh; Moonkang Choi; Kiheun Lee; Sangwoo Han; et al. (IRPS, 2024)

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND. - Ilho Myeong; Suhwan Lim; Taeyoung Kim; Sanghyun Park; Suseong Noh; Seung Min Lee; Jongho Woo; Hanseung Ko; Youngji Noh; Munkang Choi; Kiheun Lee; Sangwoo Han; et al. (IRPS, 2024)

In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND Beyond 1K Layers: Experimental Demonstration and Modeling. - Giuk Kim; Hyojun Choi; Hunbeom Shin; Sangho Lee; Sangmok Lee; Yunseok Nam; Minhyun Jung; Ilho Myeong; Kijoon Kim; Jongho Woo; Suhwan Lim; Kwangsoo Kim; et al. (VLSI Technology and Circuits, 2024)

Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate. - Zijian Zhao 001; Sola Woo; Khandker Akif Aabrar; Sharadindu Gopal Kirtania; Zhouhang Jiang; Shan Deng; Yi Xiao 008; Halid Mulaosmanovic; Stefan Dünkel; Dominik Kleimaier; Steven Soss; Sven Beyer; et al. (CoRR, 2024)

Comparative Study of Channel Materials for Ferroelectric NAND Applications. - Lance Fernandes; Prasanna Venkatesan Ravindran; Mengkun Tian; Yu-Hsin Kuo; Nashrah Afroze; Salma Soliman; Sanghyun Kang; Dyutimoy Chakraborty; Taeyoung Song; Chengyang Zhang; Kijoon Kim; Kwangyou Seo; et al. (IMW, 2025)

Investigating Read-After-Write Delay in Ferroelectric FET with Gate-Side Injection. - Sizhe Ma; Saikat Chakraborty; Yixin Qin; Zijian Zhao 001; Jiahui Duan; Moonyoung Jung; Kijoon Kim; Suhwan Lim; Kwangyou Seo; Kwangsoo Kim; Wanki Kim; Daewon Ha; et al. (IRPS, 2025)

Retention Analysis of Ferroelectric FETs with Gate-Side Injection for Vertical NAND Storage. - Yixin Qin; Saikat Chakraborty; Zijian Zhao 001; Sizhe Ma; Moonyoung Jung; Kijoon Kim; Suhwan Lim; Kwangyou Seo; Kwangsoo Kim; Wanki Kim; Daewon Ha; Vijaykrishnan Narayanan; et al. (IRPS, 2025)

Enhanced Memory Performance in Ferroelectric NAND Applications: The Role of Tunnel Dielectric Position for Robust 10-Year Retention. - Prasanna Venkatesan Ravindran; Andrea Padovani; Lance Fernandes; Priyankka Gundlapudi Ravikumar; Chinsung Park; Huy Tran; Zekai Wang; Hari Jayasankar; Amrit Garlapati; Taeyoung Song; Hang Chen; Winston Chern; et al. (IRPS, 2025)

Modeling Dynamic Interplay Between Charge Traps and Polarization for Memory Window Enhancement in Gate Injection Layers. - Minji Shon; Chinsung Park; Prasanna Venkatesan Ravindran; Lance Fernandes; Kijoon Kim; Jongho Woo; Suhwan Lim; Kwangsoo Kim; Wanki Kim; Daewon Ha; Suman Datta; Asif Khan; et al. (IRPS, 2025)