An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits. - Kyungho Ryu; Kil-Hoon Lee; Jung-Pil Lim; Jinho Kim; Han Su Pae; Junho Park; Hyun-Wook Lim; Jae-Youl Lee (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/ps Slew Rate for 8K Displays and Beyond. - Kyungho Ryu; Ji-Yong Jeong; Jung-Pil Lim; Kil-Hoon Lee; Kyongho Kim; Yongil Kwon; Seongjong Yoo; Siwoo Kim; Hyun-Wook Lim; Jae-Youl Lee (ISSCC, 2023)