A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure. - Gi-Ho Park; Kil-Whan Lee; Jae-Hyuk Lee; Tack-Don Han; Shin-Dug Kim (LCTES, 2000)

A Dual Data Cache System to Reflect the Principle of Locality Effectively. - Gi-Ho Park; Kil-Whan Lee; Tack-Don Han; Shin-Dug Kim (PDPTA, 2000)

A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors. - Woo-Chan Park; Kil-Whan Lee; Il-San Kim; Tack-Don Han; Sung-Bong Yang (ASAP, 2002)

An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors. - Woo-Chan Park; Kil-Whan Lee; Il-San Kim; Tack-Don Han; Sung-Bong Yang (IEEE Trans. Computers, 2003)

A pixel cache architecture with selective placement scheme based on z-test result. - Kil-Whan Lee; Woo-Chan Park; Il-San Kim; Tack-Don Han (Microprocess. Microsystems, 2005)

A Processor Architecture with Effective Memory System for Sort-Last Parallel Rendering. - Woo-Chan Park; Duk-Ki Yoon; Kil-Whan Lee; Il-San Kim; Kyung-Su Kim; Won-Jong Lee; Tack-Don Han; Sung-Bong Yang (ARCS, 2006)

Cooperative Cache System: A Low Power Cache System for Embedded Processors. - Gi-Ho Park; Kil-Whan Lee; Tack-Don Han; Shin-Dug Kim (IEICE Trans. Electron., 2007)

A consistency-free memory architecture for sort-last parallel rendering processors. - Woo-Chan Park; Cheong-Ghil Kim; Duk-Ki Yoon; Kil-Whan Lee; Il-San Kim; Tack-Don Han (J. Syst. Archit., 2007)