A 60-ns 16-Mb flash EEPROM with program and erase sequence controller. - Takeshi Nakayama; Shin'ichi Kobayashi; Yoshikazu Miyawaki; Yasushi Terada; Natsuo Ajika; Makoto Ohi; Hideaki Arima; Takayuki Matsukawa; Tsutomu Yoshihara; Kimio Suzuki (IEEE J. Solid State Circuits, 1991)

A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture. - Toru Shiomi; Tomohisa Wada; Shigeki Ohbayashi; Atsushi Ohba; Hiroki Honda; Yoshiyuki Ishigaki; Shiro Hine; Kenji Anami; Kimio Suzuki; Tadashi Sumi (IEEE J. Solid State Circuits, 1993)