A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine. - Kin-Chu Ho; Po-Chao Fang; Hsiang-Pang Li; Cheng-Yuan Michael Wang; Hsie-Chia Chang (ISSCC, 2013)

EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs. - Ren-Shuo Liu; Meng-Yen Chuang; Chia-Lin Yang; Cheng-Hsuan Li; Kin-Chu Ho; Hsiang-Pang Li (DAC, 2014)

A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. - Kin-Chu Ho; Chih-Lung Chen; Yen-Chin Liao; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2015)

Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality. - Ren-Shuo Liu; Meng-Yen Chuang; Chia-Lin Yang; Cheng-Hsuan Li; Kin-Chu Ho; Hsiang-Pang Li (IEEE Trans. Computers, 2016)

A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory. - Kin-Chu Ho; Chih-Lung Chen; Hsie-Chia Chang (IEEE Trans. Very Large Scale Integr. Syst., 2016)