An LDPC decoding schedule for memory access reduction. - Kiran K. Gunnam; Gwan Choi; Mark Yeary (ICASSP (5), 2004)

New optimizations for carrier synchronization in single carrier systems. - Kiran K. Gunnam; Kanu Chadha; Mark Yeary (ICASSP (5), 2005)

Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation. - Kiran K. Gunnam (2006)

VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax. - Kiran K. Gunnam; Gwan S. Choi; Mark B. Yeary; Mohammed Atiquzzaman (ICC, 2007)

Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard. - Kiran K. Gunnam; Gwan Choi; Weihuang Wang; Mark B. Yeary (ISCAS, 2007)

A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes. - Kiran K. Gunnam; Gwan S. Choi; Mark B. Yeary (VLSI Design, 2007)

Next generation iterative LDPC solutions for magnetic recording storage. - Kiran K. Gunnam; Gwan S. Choi; Mark B. Yeary; Shaohua Yang; Yuanxing Lee (ACSCC, 2008)

Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels. - Weihuang Wang; Gwan S. Choi; Kiran K. Gunnam (VLSI Design, 2009)

Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes". - Kiran K. Gunnam; Gwan S. Choi; Mark B. Yeary (EURASIP J. Embed. Syst., 2009)

Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels. - Weihuang Wang; Euncheol Kim; Kiran K. Gunnam; Gwan S. Choi (J. Low Power Electron., 2009)

Trellis based Extended Min-Sum for decoding nonbinary LDPC codes. - Erbao Li; Kiran K. Gunnam; David Declercq (ISWCS, 2011)

Low latency T-EMS decoder for non-binary LDPC codes. - Erbao Li; Francisco Garcia-Herrero; David Declercq; Kiran K. Gunnam; Jesus Omar Lacruz; Javier Valls (ACSSC, 2013)

Trellis-Based Extended Min-Sum Algorithm for Non-Binary LDPC Codes and its Hardware Structure. - Erbao Li; David Declercq; Kiran K. Gunnam (IEEE Trans. Commun., 2013)

An efficient reconfigurable hardware accelerator for convolutional neural networks. - Anaam Ansari; Kiran K. Gunnam; Tokunbo Ogunfunmi (ACSSC, 2017)

Adaptive Multi-Precision Inference for Large-Scale AI Using IEEE P3109 FP8. - Arnav Ramamoorthy; Kiran K. Gunnam (ISVLSI, 2025)