CoDG-ReRAM: An Algorithm-Hardware Co-design to Accelerate Semi-Structured GNNs on ReRAM. - Yixuan Luo; Payman Behnam; Kiran Thorat; Zhuo Liu; Hongwu Peng; Shaoyi Huang; Shu Zhou; Omer Khan; Alexey Tumanov; Caiwen Ding; Tong Geng (ICCD, 2022)

LinGCN: Structural Linearized Graph Convolutional Network for Homomorphically Encrypted Inference. - Hongwu Peng; Ran Ran; Yukui Luo; Jiahui Zhao; Shaoyi Huang; Kiran Thorat; Tong Geng; Chenghong Wang; Xiaolin Xu 001; Wujie Wen; Caiwen Ding (NeurIPS, 2023)

Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis. - Kiran Thorat; Jiahui Zhao; Yaotian Liu; Hongwu Peng; Xi Xie; Bin Lei; Jeff Zhang 001; Caiwen Ding (CoRR, 2023)

HiVeGen - Hierarchical LLM-based Verilog Generation for Scalable Chip Design. - Jinwei Tang; Jiayin Qin; Kiran Thorat; Chen Tian 001; Yu Cao; Yang Zhao; Caiwen Ding (CoRR, 2024)

TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs. - Kiran Thorat; Amit Hasan 001; Caiwen Ding; Zhijie Shi (CoRR, 2025)