Optical and Electrical Testing of Latchup in I/O Interface Circuits. - Franco Stellari; Peilin Song; Moyra K. McManus; Robert Gauthier 002; Alan J. Weger; Kiran V. Chatty; Mujahid Muhammad; Pia N. Sanda (ITC, 2003)

Latchup Analysis Using Emission Microscopy. - Franco Stellari; Peilin Song; Moyra K. McManus; Alan J. Weger; Robert Gauthier 002; Kiran V. Chatty; Mujahid Muhammad; Pia N. Sanda; Philip Wu; Steven C. Wilson (Microelectron. Reliab., 2003)

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant. - David Alvarez; Michel J. Abou-Khalil; Christian Russ; Kiran V. Chatty; Robert Gauthier 002; D. Kontos; Junjun Li; Christopher Seguin; Ralph Halbach (Microelectron. Reliab., 2006)

Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs. - Ciaran J. Brennan; Kiran V. Chatty; Jeff Sloan; Paul Dunn; Mujahid Muhammad; Robert Gauthier 002 (Microelectron. Reliab., 2007)

Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs. - Ciaran J. Brennan; Shunhua Chang; Min Woo; Kiran V. Chatty; Robert Gauthier 002 (Microelectron. Reliab., 2007)

Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology. - David Alvarez; Kiran V. Chatty; Christian Russ; Michel J. Abou-Khalil; Junjun Li; Robert Gauthier 002; Kai Esmark; Ralph Halbach; Christopher Seguin (Microelectron. Reliab., 2009)

Reliability aspects of gate oxide under ESD pulse stress. - Adrien Ille; Wolfgang Stadler; Thomas Pompl; Harald Gossner; Tilo Brodbeck; Kai Esmark; Philipp Riess; David Alvarez; Kiran V. Chatty; Robert Gauthier 002; Alain Bravaix (Microelectron. Reliab., 2009)

Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology. - Tommaso Cilento; M. Schenkel; C. Yun; R. Mishra; Junjun Li; Kiran V. Chatty; Robert Gauthier 002 (Microelectron. Reliab., 2010)