An Iterative Technique for Runtime Efficient Hardware-Software Partitioning. - Deshya Wijesundera; Kisaru Liyanage; Alok Prakash; Thambipillai Srikanthan; Thilina Perera (FPT, 2019)

Technique for Vendor and Device Agnostic Hardware Area-Time Estimation. - Deshya Wijesundera; Kushagra Shah; Kisaru Liyanage; Alok Prakash; Thambipillai Srikanthan; Thilina Perera (ARC, 2020)

Invited: Algorithms and Architectures for Accelerating Long Read Sequence Analysis. - Hasindu Gamaarachchi; Kisaru Liyanage; Sri Parameswaran (DAC, 2023)

Cross Layer Design Using HW/SW Co-Design and HLS to Accelerate Chaining in Genomic Analysis. - Kisaru Liyanage; Hasindu Gamaarachchi; Roshan G. Ragel; Sri Parameswaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Accelerating Chaining in Genomic Analysis Using RISC- V Custom Instructions. - Kisaru Liyanage; Hasindu Gamaarachchi; Hassaan Saadat; Tuo Li 001; Hiruna Samarakoon; Sri Parameswaran (DATE, 2024)

Acceleration of DNA Sequence Alignment Tools Using Hardware-Software Co-Design. - Kisaru Liyanage (2024)