25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation. - Tae-Young Oh; Hoeju Chung; Young-Chul Cho; Jang-Woo Ryu; Kiwon Lee; Changyoung Lee; Jin-Il Lee; Hyoung-Joo Kim 002; Min-Soo Jang; Gong-Heum Han; Kihan Kim; Daesik Moon; et al. (ISSCC, 2014)

An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory. - Dongsuk Shin; Hakbeom Jang; Kiseok Oh; Jae W. Lee (ACM Trans. Embed. Comput. Syst., 2022)