ALIGN: Open-Source Analog Layout Automation from the Ground Up. - Kishor Kunal; Meghna Madhusudan; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Desmond A. Kirkpatrick; Sachin S. Sapatnekar (DAC, 2019)

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. - Kishor Kunal; Tonmoy Dhar; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2020)

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ICCAD, 2020)

A general approach for identifying hierarchical symmetry constraints for analog circuit layout. - Kishor Kunal; Jitesh Poojary; Tonmoy Dhar; Meghna Madhusudan; Ramesh Harjani; Sachin S. Sapatnekar (ICCAD, 2020)

Learning from Experience: Applying ML to Analog Circuit Design. - Kishor Kunal; Tonmoy Dhar; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Sachin S. Sapatnekar (ISPD, 2020)

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. - Tonmoy Dhar; Jitesh Poojary; Yaguang Li; Kishor Kunal; Meghna Madhusudan; Arvind K. Sharma; Susmita Dey Manasi; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (ASP-DAC, 2021)

BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology. - Vidya A. Chhabria; Kishor Kunal; Masoud Zabihi; Sachin S. Sapatnekar (ICCAD, 2021)

Machine Learning Techniques in Analog Layout Automation. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ISPD, 2021)

GNNIE: GNN Inference Engine with Load-balancing and Graph-Specific Caching. - Sudipta Mondal; Susmita Dey Manasi; Kishor Kunal; Sachin S. Sapatnekar (CoRR, 2021)

ALIGN: A System for Automating Analog Layout. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Desmond A. Kirkpatrick; Parijat Mukherjee; et al. (IEEE Des. Test, 2021)

GNNIE: GNN inference engine with load-balancing and graph-specific caching. - Sudipta Mondal; Susmita Dey Manasi; Kishor Kunal; Ramprasath S 001; Sachin S. Sapatnekar (DAC, 2022)

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. - Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Ramprasath S 001; Kishor Kunal; Sachin S. Sapatnekar; Ramesh Harjani (ESSDERC, 2023)

A Multicore GNN Training Accelerator. - Sudipta Mondal; Ramprasath S 001; Ziqing Zeng; Kishor Kunal; Sachin S. Sapatnekar (ISLPED, 2023)

ChipNeMo: Domain-Adapted LLMs for Chip Design. - Mingjie Liu; Teodor-Dumitru Ene; Robert Kirby 001; Chris Cheng; Nathaniel Ross Pinckney; Rongjian Liang; Jonah Alben; Himyanshu Anand; Sanmitra Banerjee; Ismet Bayraktaroglu; Bonita Bhaskaran; Bryan Catanzaro; et al. (CoRR, 2023)

GNN-Based Hierarchical Annotation for Analog Circuits. - Kishor Kunal; Tonmoy Dhar; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching. - Sudipta Mondal; Susmita Dey Manasi; Kishor Kunal; Ramprasath S 001; Ziqing Zeng; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Reinforcing the Connection between Analog Design and EDA (Invited Paper). - Kishor Kunal; Meghna Madhusudan; Jitesh Poojary; S. Ramprasath 001; Arvind K. Sharma; Ramesh Harjani; Sachin S. Sapatnekar (ASPDAC, 2024)

Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. - Kishor Kunal; Jitesh Poojary; S. Ramprasath 001; Ramesh Harjani; Sachin S. Sapatnekar (ASPDAC, 2024)

Generative Methods in EDA: Innovations in Dataset Generation and EDA Tool Assistants. - Vidya A. Chhabria; Bing-Yue Wu; Utsav Sharma; Kishor Kunal; Austin Rovinski; Sachin S. Sapatnekar (ICCAD, 2024)

Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance. - Amit Sharma; Teodor-Dumitru Ene; Kishor Kunal; Mingjie Liu; Zafar Hasan; Haoxing Ren (CoRR, 2024)

LEGO-Size: LLM-Enhanced GPU-Optimized Signoff-Accurate Differentiable VLSI Gate Sizing in Advanced Nodes. - Yi-Chen Lu; Kishor Kunal; Geraldo Pradipta; Rongjian Liang; Ravikishore Gandikota; Haoxing Ren (ISPD, 2025)

JARVIS: A Multi-Agent Code Assistant for High-Quality EDA Script Generation. - Ghasem Pasandi; Kishor Kunal; Varun Tej; Kunjal Shan; Hanfei Sun; Sumit Jain; Chunhui Li; Chenhui Deng; Teodor-Dumitru Ene; Haoxing Ren; Sreedhar Pratty (CoRR, 2025)