A technique to determine power-efficient, high-performance superscalar processors. - Thomas M. Conte; Kishore N. Menezes; Sumedh W. Sathaye (HICSS (1), 1995)

Optimization of Instruction Fetch Mechanisms for High Issue Rates. - Thomas M. Conte; Kishore N. Menezes; Patrick M. Mills; Burzin A. Patel (ISCA, 1995)

Reducing State Loss For Effective Trace Sampling of Superscalar Processors. - Thomas M. Conte; Mary Ann Hirsch; Kishore N. Menezes (ICCD, 1996)

Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. - Thomas M. Conte; Sanjeev Banerjia; Sergei Y. Larin; Kishore N. Menezes; Sumedh W. Sathaye (MICRO, 1996)

Accurate and Practical Profile-driven Compilation Using the Profile Buffer. - Thomas M. Conte; Kishore N. Menezes; Mary Ann Hirsch (MICRO, 1996)

Hardware-Based Profiling: An Effective Technique for Profile-Driven Optimization. - Thomas M. Conte; Burzin A. Patel; Kishore N. Menezes; J. Stan Cox (Int. J. Parallel Program., 1996)

Path Prediction for High Issue-Rate Processors. - Kishore N. Menezes; Sumedh W. Sathaye; Thomas M. Conte (IEEE PACT, 1997)

A Fast Interrupt Handling Scheme for VLIW Processors. - Emre Özer 001; Sumedh W. Sathaye; Kishore N. Menezes; Sanjeev Banerjia; Matthew D. Jennings; Thomas M. Conte (IEEE PACT, 1998)

MPS: Miss-Path Scheduling for Multiple-Issue Processors. - Sanjeev Banerjia; Sumedh W. Sathaye; Kishore N. Menezes; Thomas M. Conte (IEEE Trans. Computers, 1998)

Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs. - Jay Bharadwaj; Kishore N. Menezes; Chris McKinsey (J. Instr. Level Parallelism, 2000)

The Intel IA-64 Compiler Code Generator. - Jay Bharadwaj; William Y. Chen; Weihaw Chuang; Gerolf Hoflehner; Kishore N. Menezes; Kalyan Muthukumar; Jim Pierce (IEEE Micro, 2000)

System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. - Thomas M. Conte; Kishore N. Menezes; Sumedh W. Sathaye; Mark C. Toburen (IEEE Trans. Very Large Scale Integr. Syst., 2000)