Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems. - Sangyeun Cho; Lei Jin 002; Kiyeon Lee (RTCSA, 2007)

TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation. - Sangyeun Cho; Socrates Demetriades; Shayne Evans; Lei Jin 002; Hyunjin Lee; Kiyeon Lee; Michael Moeng (ICPP, 2008)

Accurately approximating superscalar processor performance from traces. - Kiyeon Lee; Shayne Evans; Sangyeun Cho (ISPASS, 2009)

An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor. - Taecheol Oh; Hyunjin Lee; Kiyeon Lee; Sangyeun Cho (ISVLSI, 2009)

Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach. - Hyunjin Lee; Lei Jin 002; Kiyeon Lee; Socrates Demetriades; Michael Moeng; Sangyeun Cho (Softw. Pract. Exp., 2010)

In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces. - Kiyeon Lee; Sangyeun Cho (MASCOTS, 2011)

An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing. - Taecheol Oh; Kiyeon Lee; Sangyeun Cho (MASCOTS, 2011)

Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors. - Kiyeon Lee; Moo-Kyoung Chung; Soojung Ryu; Yeon-Gon Cho; Sangyeun Cho (ICCD, 2012)

Accurately modeling superscalar processor performance with reduced trace. - Kiyeon Lee; Sangyeun Cho (J. Parallel Distributed Comput., 2013)

Scattering and Nonscattering of the Hartree-Type Nonlinear Dirac System at Critical Regularity. - Yonggeun Cho; Seokchang Hong; Kiyeon Lee (SIAM J. Math. Anal., 2023)