An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters. - Masataka Matsui; Hiroshi Momose; Yukihiro Urakawa; Takeo Maeda; Azuma Suzuki; Nobuaki Urakawa; Katsuhiko Sato; Jun'ichi Matsunaga; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1989)

A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell. - Takayuki Ootani; Shigeyuki Hayakawa; Masakazu Kakumu; Akira Aona; Masaaki Kinugawa; Hideki Takeuchi; Kazuhiro Noguchi; Tomoaki Yabe; Katsuhiko Sato; Kenji Maeguchi; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1990)

Consideration of poly-Si loaded cell capacity limits for low-power and high-speed SRAMs. - Hideo Kato; Katsuhiko Sato; Masataka Matsui; H. Shibata; K. Hashimoto; Takayuki Ootani; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1992)

SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober. - Hideo Kato; Masataka Matsui; Katsuhiko Sato; H. Shibata; K. Hashimoto; Takayuki Ootani; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1997)