A built-in Hamming code ECC circuit for DRAMs. - Kiyohiro Furutani; Kazutami Arimoto; Hiroshi Miyamoto; Toshifumi Kobayashi; Kenichi Yasuda; Koichiro Mashiko (IEEE J. Solid State Circuits, 1989)

A pipelined microprocessor for logic programming languages. - Hiroshi Nakashima; Yasutaka Takeda; Katsuto Nakajima; Hideki Andou; Kiyohiro Furutani (ICCD, 1990)

A speed-enhanced DRAM array architecture with embedded ECC. - Kazutami Arimoto; Yoshio Matsuda; Kiyohiro Furutani; Masaki Tsukude; Tsukasa Ooishi; Koichiro Mashiko; Kuzuyasu Fujishima (IEEE J. Solid State Circuits, 1990)

A VLSI chip set for a large-scale parallel inference machine: PIM/m. - Hirohisa Machida; Hideki Ando; Kenichi Yasuda; Kiyohiro Furutani; Yukihiro Yamashita; Hiroshi Nakashima; Yasutaka Takeda; Katsuto Nakajima; Masayoshi Sakao; Masao Nakaya (IEEE J. Solid State Circuits, 1993)

An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM. - Kiyohiro Furutani; Hiroshi Miyamoto; Yoshikazu Morooka; Makoto Suwa; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1994)

An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs. - Yasuhiko Tsukikawa; Takeshi Kajimoto; Yasuhiko Okasaka; Yoshikazu Morooka; Kiyohiro Furutani; Hiroshi Miyamoto; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1994)

An automatic temperature compensation of internal sense ground for subquarter micron DRAM's. - Tsukasa Ooishi; Yuichiro Komiya; Kei Hamade; Mho Asakura; Kenichi Yasuda; Kiyohiro Furutani; Hideto Hidaka; Hiroshi Miyamoto; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1995)

A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories. - Tsukasa Ooishi; Yuichiro Komiya; Kei Hamade; Mikio Asakura; Kenichi Yasuda; Kiyohiro Furutani; Tetsuo Kato; Hideto Hidaka; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1996)

A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. - Shigehiro Kuge; Tetsuo Kato; Kiyohiro Furutani; Shigeru Kikuda; Katsuyoshi Mitsui; Takeshi Hamamoto; Jun Setogawa; Kei Hamade; Yuichiro Komiya; Satoshi Kawasaki; Takashi Kono; Teruhiko Amano; et al. (IEEE J. Solid State Circuits, 2000)

A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. - Takeshi Hamamoto; Kiyohiro Furutani; Takashi Kubo; Satoshi Kawasaki; Hironori Iga; Takashi Kono; Yasuhiro Konishi; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 2004)

Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories. - Kiyohiro Furutani; Takeshi Hamamoto; Takeo Miki; Masaya Nakano; Takashi Kono; Shigeru Kikuda; Yasuhiro Konishi; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)