A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure. - Akira Umezawa; Shigeru Atsumi; Masao Kuriyama; Hironori Banba; Ken-ichi Imamiya; Kiyomi Naruke; Seiji Yamada; Etsushi Obi; Masamitsu Oshikiri; Tomoko Suzuki; Sumio Tanaka (IEEE J. Solid State Circuits, 1992)

A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation. - Shigeru Atsumi; Masao Kuriyama; Akira Umezawa; Hironori Banba; Kiyomi Naruke; Seiji Yamada; Yoichi Ohshima; Masamitsu Oshikiri; Yohei Hiura; Tomoko Yamane; Kuniyoshi Yoshikawa (IEEE J. Solid State Circuits, 1994)

A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller. - Toru Tanzawa; Akira Umezawa; Tadayuki Taura; Hitoshi Shiga; Tokumasa Hara; Yoshinori Takano; Takeshi Miyaba; Naoya Tokiwa; Kentaro Watanabe; Hiroshi Watanabe; Kazunori Masuda; Kiyomi Naruke; et al. (IEEE J. Solid State Circuits, 2002)

A 151mm2 64Gb MLC NAND flash memory in 24nm CMOS technology. - Koichi Fukuda; Yoshihisa Watanabe; Eiichi Makino; Koichi Kawakami; Jumpei Sato; Teruo Takagiwa; Naoaki Kanagawa; Hitoshi Shiga; Naoya Tokiwa; Yoshihiko Shindo; Toshiaki Edahiro; Takeshi Ogawa; et al. (ISSCC, 2011)

A 151-mm2 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology. - Koichi Fukuda; Yoshihisa Watanabe; Eiichi Makino; Koichi Kawakami; Jumpei Sato; Teruo Takagiwa; Naoaki Kanagawa; Hitoshi Shiga; Naoya Tokiwa; Yoshihiko Shindo; Takeshi Ogawa; Toshiaki Edahiro; et al. (IEEE J. Solid State Circuits, 2012)