A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques. - Goro Kitsukawa; Kiyoo Itoh 001; Ryoichi Hori; Yoshiki Kawajiri; Takao Watanabe; Takayuki Kawahara; Tetsuro Matsumoto; Yutaka Kobayashi (IEEE J. Solid State Circuits, 1989)

Comparison of CMOS and BiCMOS 1-Mbit DRAM performance. - Takao Watanabe; Goro Kitsukawa; Yoshiki Kawajiri; Kiyoo Itoh 001; Ryoichi Hori; Yoshiaki Ouchi; Takayuki Kawahara; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1989)

New DRAM noise generation under half-Vcc precharge and its reduction using a transposed amplifier. - Masakazu Aoki; Shin'ichi Ikenaga; Yoshinobu Nakagome; Masashi Horiguchi; Yasushi Kawase; Yoshifumi Kawamoto; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1989)

A 1.5-V DRAM for battery-based applications. - Masakazu Aoki; Jun Etoh; Kiyoo Itoh 001; Shin Kimura; Yoshifumi Kawamoto (IEEE J. Solid State Circuits, 1989)

Substrate current reduction techniques for BiCMOS DRAM. - Takayuki Kawahara; Goro Kitsukawa; Hisayuki Higuchi; Yoshiki Kawajiri; Takao Watanabe; Kiyoo Itoh 001; Ryoichi Hori; Yutaka Kobayashi; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1989)

Trends in megabit DRAM circuit design. - Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1990)

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier. - Masashi Horiguchi; Masakazu Aoki; Jun Etoh; Hitoshi Tanaka; Shin'ichi Ikenaga; Kiyoo Itoh 001; Kazuhiko Kajigaya; Hiroaki Kotani; Kazuyoshi Ohshima; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1990)

A 23-ns 1-Mb BiCMOS DRAM. - Goro Kitsukawa; Kazumasa Yanagisawa; Yutaka Kobayashi; Yoshitaka Kinoshita; Tatsuyuki Ohta; Tetsu Udagawa; Hitoshi Miwa; Hiroyuki Miyazawa; Yoshiki Kawajiri; Yoshiaki Ouchi; Hiromi Tsukada; Tetsuro Matsumoto; et al. (IEEE J. Solid State Circuits, 1990)

A flexible redundancy technique for high-density DRAMs. - Masashi Horiguchi; Jun Etoh; Masakazu Aoki; Kiyoo Itoh 001; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1991)

An experimental 1.5-V 64-Mb DRAM. - Yoshinobu Nakagome; Hitoshi Tanaka; Kan Takeuchi; Eiji Kume; Yasushi Watanabe; Toru Kaga; Yoshifumi Kawamoto; Fumio Murai; Ryuichi Izawa; Digh Hisamoto; Teruaki Kisu; Takashi Nishida; et al. (IEEE J. Solid State Circuits, 1991)

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM. - Yoshinobu Nakagome; Kiyoo Itoh 001; Kan Takeuchi; Eiji Kume; Hitoshi Tanaka; Masanori Isoda; Tatsunori Musha; Toru Kaga; Teruaki Kisu; Takashi Nishida; Yoshifumi Kawamoto; Masakazu Aoki (IEEE J. Solid State Circuits, 1991)

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's. - Takayuki Kawahara; Yoshiki Kawajiri; Goro Kitsukawa; Yoshinobu Nakagome; Kazuhiko Sagara; Yoshifumi Kawamoto; Takesada Akiba; Shisei Kato; Yasushi Kawase; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1991)

A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture. - Katsutaka Kimura; Takeshi Sakata; Kiyoo Itoh 001; Toru Kaga; Takashi Nishida; Yoshifumi Kawamoto (IEEE J. Solid State Circuits, 1991)

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's. - Takayuki Kawahara; Yoshiki Kawajiri; Goro Kitsukawa; Kazuhiko Sagara; Yoshifumi Kawamoto; Takesada Akiba; Shisei Kato; Yasushi Kawase; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1992)

A single 1.5-V digital chip for a 106 synapse neural network. - Takao Watanabe; Katsutaka Kimura; Masakazu Aoki; Takeshi Sakata; Kiyoo Ito (IEEE Trans. Neural Networks, 1993)

Sub-1-V swing internal bus architecture for future low-power ULSIs. - Yoshinobu Nakagome; Kiyoo Itoh 001; Masanori Isoda; Kan Takeuchi; Masakazu Aoki (IEEE J. Solid State Circuits, 1993)

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays. - Takayuki Kawahara; Takeshi Sakata; Kiyoo Itoh 001; Yoshiki Kawajiri; Takesada Akiba; Goro Kitsukawa; Masakazu Aoki (IEEE J. Solid State Circuits, 1993)

Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's. - Masashi Horiguchi; Takeshi Sakata; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1993)

Subthreshold-current reduction circuits for multi-gigabit DRAM's. - Takeshi Sakata; Kiyoo Itoh 001; Masashi Horiguchi; Masakazu Aoki (IEEE J. Solid State Circuits, 1994)

Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's. - Takeshi Sakata; Kiyoo Itoh 001; Masashi Horiguchi; Masakazu Aoki (IEEE J. Solid State Circuits, 1994)

Trends in low-power RAM circuit technologies. - Kiyoo Itoh 001; Katsuro Sasaki; Yoshinobu Nakagome (Proc. IEEE, 1995)

Limitations and challenges of multigigabit DRAM chip design. - Kiyoo Itoh 001; Yoshinobu Nakagome; Shin'ichiro Kimura; Takao Watanabe (IEEE J. Solid State Circuits, 1997)

Low-Voltage Embedded-RAM Technology: Present and Future. - Kiyoo Itoh 001; Hiroyuki Mizuno (VLSI-SOC, 2001)

A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. - Tsugio Takahashi; Tomonori Sekiguchi; Riichiro Takemura; Seiji Narui; Hiroki Fujisawa; Shinichi Miyatake; Makoto Morino; Koji Arai; Satoru Yamada; Shoji Shukuri; Masayuki Nakamura; Yoshitaka Tadaki; et al. (IEEE J. Solid State Circuits, 2001)

Low-voltage memories for power-aware systems. - Kiyoo Itoh 001 (ISLPED, 2002)

Trends in Ultralow-Voltage RAM Technology. - Kiyoo Itoh 001 (PATMOS, 2002)

A low-impedance open-bitline array for multigigabit DRAM. - Tomonori Sekiguchi; Kiyoo Itoh 001; Tsugio Takahashi; Masahiro Sugaya; Hiroki Fujisawa; Masayuki Nakamura; Kazuhiko Kajigaya; Katsutaka Kimura (IEEE J. Solid State Circuits, 2002)

Review and future prospects of low-voltage RAM circuits. - Yoshinobu Nakagome; Masashi Horiguchi; Takayuki Kawahara; Kiyoo Itoh 001 (IBM J. Res. Dev., 2003)

Reviews and future prospects of low-voltage embedded RAMs. - Kiyoo Itoh 001; Kenichi Osada; Takayda Kawahara (CICC, 2004)

Low-Voltage Embedded RAMs - Current Status and Future Trends. - Kiyoo Itoh 001; Kenichi Osada; Takayuki Kawahara (PATMOS, 2004)

Ultra-low voltage nano-scale embedded RAMs. - Kiyoo Itoh 001; Masashi Horiguchi; Takayuki Kawahara (ISCAS, 2006)

A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers. - Riichiro Takemura; Kiyoo Itoh 001; Tomonori Sekiguchi (ISLPED, 2006)

Low-voltage limitations of memory-rich nano-scale CMOS LSIs. - Kiyoo Itoh 001; Masashi Horiguchi; Masanao Yamaoka (ESSCIRC, 2007)

Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. - Kiyoo Itoh 001; Masanao Yamaoka; Takayuki Kawahara (ACM Great Lakes Symposium on VLSI, 2007)

Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs. - Kiyoo Itoh 001 (ICECS, 2007)

Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs. - Kiyoo Itoh 001; Riichiro Takemura (ICECS, 2007)

Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation. - Riichiro Takemura; Kiyoo Itoh 001; Tomonori Sekiguchi; Satoru Akiyama; Satoru Hanzawa; Kazuhiko Kajigaya; Takayuki Kawahara (IEICE Trans. Electron., 2007)

Ultra-Low Voltage Nano-Scale Memories - Kiyoo Itoh 001; Masashi Horiguchi; Hitoshi Tanaka (Springer, 2007)

Memory at VLSI Circuits Symposium. - Kiyoo Itoh 001; Hideaki Kurata; Kenichi Osada; Tomonori Sekiguchi (IEEE J. Solid State Circuits, 2008)

Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. - Kiyoo Itoh 001 (ISLPED, 2009)

Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. - Satoru Akiyama; Tomonori Sekiguchi; Riichiro Takemura; Akira Kotabe; Kiyoo Itoh 001 (ISSCC, 2009)

Adaptive circuits for the 0.5-V nanoscale CMOS era. - Kiyoo Itoh 001 (ISSCC, 2009)

Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs. - Kiyoo Itoh 001 (PATMOS, 2010)

Adaptive Circuits for the 0.5-V Nanoscale CMOS Era. - Kiyoo Itoh 001; Masanao Yamaoka; Takashi Oshima (IEICE Trans. Electron., 2010)

Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. - Akira Kotabe; Kiyoo Itoh 001; Riichiro Takemura; Ryuta Tsuchiya; Masashi Horiguchi (CICC, 2011)

Beyond the horizon: The next 10x reduction in power - Challenges and solutions. - Jan M. Rabaey; Hugo De Man; Mark Horowitz; Takayasu Sakurai; Jack Sun; Dan Dobberpuhl; Kiyoo Itoh 001; Philippe Magarshack; Asad A. Abidi; Hermann Eul (ISSCC, 2011)

Embedded Memories: Progress and a Look into the Future. - Kiyoo Itoh 001 (IEEE Des. Test Comput., 2011)

Nanoscale Memory Repair - Masashi Horiguchi; Kiyoo Itoh 001 (Springer, 2011)

A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing. - Satoru Akiyama; Riichiro Takemura; Tomonori Sekiguchi; Akira Kotabe; Kiyoo Itoh 001 (IEICE Trans. Electron., 2012)

0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs. - Akira Kotabe; Kiyoo Itoh 001; Riichiro Takemura (IEICE Trans. Electron., 2012)

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays. - Akira Kotabe; Riichiro Takemura; Yoshimitsu Yanagawa; Tomonori Sekiguchi; Kiyoo Itoh 001 (IEICE Trans. Electron., 2012)