Multiple-Valued Logic Minimization by Genetic Algorithms. - Yutaka Hata; Kiyoshi Hayase; Takahiro Hozumi; Naotake Kamiura; Kazuharu Yamato (ISMVL, 1997)

A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory. - Satoshi Kaneko; Hiroyuki Kondo; Norio Masui; Koichi Ishimi; Teruyuki Itou; Masayuki Satou; Naoto Okumura; Yukari Takata; Hirokazu Takata; Mamoru Sakugawa; Takashi Higuchi; Sugako Ohtani; et al. (IEEE J. Solid State Circuits, 2004)

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. - Yutaka Yoshida; Tatsuya Kamei; Kiyoshi Hayase; Shinichi Shibahara; Osamu Nishii; Toshihiro Hattori; Atsushi Hasegawa; Masashi Takada; Naohiko Irie; Kunio Uchiyama; Toshihiko Odaka; Kiwamu Takada; et al. (ISSCC, 2007)

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. - Masayuki Ito; Toshihiro Hattori; Yutaka Yoshida; Kiyoshi Hayase; Tomoichi Hayashi; Osamu Nishii; Yoshihiko Yasu; Atsushi Hasegawa; Masashi Takada; Hiroyuki Mizuno; Kunio Uchiyama; Toshihiko Odaka; et al. (ISSCC, 2008)