Hardware Organization of a Low Level Parallel Processor. - Shinji Tomita; Kiyoshi Shibayama; Shigeru Oyanagi; Hiroshi Hagiwara (IFIP Congress, 1977)

Performance Evaluation and Improvement of a Dynamically Microprogrammable Computer with Low-Level Parallelism. - Kiyoshi Shibayama; Shinji Tomita; Hiroshi Hagiwara; Katsuhiro Yamazaki; Toshiaki Kitamura (IFIP Congress, 1980)

Performance evaluation and improvement of a dynamically microprogrammable computer with low-level parallelism. - Shinji Tomita; Kiyoshi Shibayama; Toshiaki Kitamura; Hiroshi Hagiwara (MICRO, 1980)

A Dynamically Microprogammable Computer with Low-Level Parallelism. - Hiroshi Hagiwara; Shinji Tomita; Shigeru Oyanagi; Kiyoshi Shibayama (IEEE Trans. Computers, 1980)

A User-Microprogrammable, Local Host Computer With Low-Level Parallelism - Shinji Tomita; Kiyoshi Shibayama; Toshiaki Kitamura; Toshiyuki Nakata 001; Hiroshi Hagiwara (ISCA, 1983)

A Computer with Low-Level Parallelism QA-2: Its Applications to 3-D Graphics and Prolog/Lisp Machines. - Shinji Tomita; Kiyoshi Shibayama; Toshiyuki Nakata 001; Shinji Yuasa; Hiroshi Hagiwara (ISCA, 1986)

KPR: A Logic Programming Language-Oriented Parallel Machine. - Kiyoshi Shibayama; Masaaki Yamamoto; Hiroaki Hirata; Yasushi Konoh; Takanori Sanetoh; Hiroshi Hagiwara (LP, 1987)

Evaluation of a data preload mechanism for a linked list structure. - Shuji Yamamura; Tadafumi Kadota; Hiroaki Hirata; Haruo Niimi; Kiyoshi Shibayama (Syst. Comput. Jpn., 2002)

Performance evaluation of dynamic load balancing scheme with load prediction mechanism using the load growing acceleration for massively parallel computers. - Atsushi Nunome; Hiroaki Hirata; Haruo Niimi; Kiyoshi Shibayama (Syst. Comput. Jpn., 2004)

Development of an e-learning back-end system for code assessment in elementary programming practice. - Atsushi Nunome; Hiroaki Hirata; Masayuki Fukuzawa; Kiyoshi Shibayama (SIGUCCS, 2010)

A Lazy-Updating Snoop Cache Protocol for Transactional Memory. - Sekai Ichii; Atsushi Nunome; Hiroaki Hirata; Kiyoshi Shibayama (IIAI-AAI, 2014)

Hardware Transactional Memory with Delayed-Committing. - Sekai Ichii; Saki Tashiro; Atsushi Nunome; Hiroaki Hirata; Kiyoshi Shibayama (ACIT-CSI, 2015)

An Information Propagation Scheme for an Autonomous Distributed Storage System in iSCSI Environment. - Shingo Shimano; Atsushi Nunome; Hiroaki Hirata; Kiyoshi Shibayama (ACIT-CSI, 2015)

A Large-Scale Speculation for the Thread-Level Parallelization. - Yuki Shoji; Atsushi Nunome; Hiroaki Hirata; Kiyoshi Shibayama (ACIT-CSI, 2015)

A Distributed Storage System with Dynamic Tiering for iSCSI Environment. - Atsushi Nunome; Hiroaki Hirata; Kiyoshi Shibayama (Int. J. Networked Distributed Comput., 2015)

Speculative memory: An architectural support for explicit speculations in multithreaded programming. - Hiroaki Hirata; Atsushi Nunome; Kiyoshi Shibayama (ICIS, 2016)

An interval control method for status propagation in an autonomous distributed storage system. - Atsushi Nunome; Hiroaki Hirata; Kiyoshi Shibayama (ICIS, 2016)

A software implementation of speculative memory. - Kohei Fujisawa; Atsushi Nunome; Kiyoshi Shibayama; Hiroaki Hirata (SNPD, 2017)

Performance evaluation of delayed-committing transactional memory. - Sekai Ichii; Shohei Hayashi; Atsushi Nunome; Hiroaki Hirata; Kiyoshi Shibayama (SNPD, 2017)

An autonomous configuration scheme of storage tiers for distributed file system. - Shingo Shimano; Atsushi Nunome; Yuta Yokoi; Kiyoshi Shibayama; Hiroaki Hirata (SNPD, 2017)

Design Space Exploration for Implementing a Software-Based Speculative Memory System. - Kohei Fujisawa; Atsushi Nunome; Kiyoshi Shibayama; Hiroaki Hirata (Int. J. Softw. Innov., 2018)