A 5-ns 1-Mb ECL BiCMOS SRAM. - Masahide Takada; Kazuyuki Nakamura; Toshio Takeshima; Koichiro Furuta; Tohru Yamazaki; Kiyotaka Imai; Susumu Ohi; Yumi Sekine; Yukio Minato; Hisamitsu Kimuto (IEEE J. Solid State Circuits, 1990)

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors. - Hitoshi Okamura; Hideo Toyoshima; Koichi Takeda; Takashi Oguri; Satoshi Nakamura; Masahide Takada; Kiyotaka Imai; Yasushi Kinoshita; Hiroshi Yoshida; Tom Yamazaki (IEEE J. Solid State Circuits, 1995)

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump. - Hitoshi Okamura; Takao Atsumo; Koichi Takeda; Masahide Takada; Kiyotaka Imai; Yasushi Kinoshita; Tom Yamazaki (IEEE J. Solid State Circuits, 1996)

A unified MOSFET channel charge model for device modeling in circuit simulation. - Yuhua Cheng; Kai Chen 002; Kiyotaka Imai; Chenming Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. - Koichiro Minami; Muneo Fukaishi; Masayuki Mizuno; Hideaki Onishi; Kenji Noda; Kiyotaka Imai; Tadahiko Horiuchi; Hiroshi Yamaguchi; Takanori Sato; Kazuyuki Nakamura; Masakazu Yaniashina (CICC, 2001)

Device technology for body biasing scheme. - Kiyotaka Imai; Yasushi Yamagata; Sadaaki Masuoka; Naohiko Kimuzuka; Yuri Yasuda; Mitsuhiro Togo; Masahiro Ikeda; Yasutaka Nakashiba (ISCAS (1), 2005)