A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier. - Katsuro Sasaki; Koichiro Ishibashi; Kiyotsugu Ueda; Kunihiro Komiyaji; Toshiaki Yamanaka; Naotaka Hashimoto; Hiroshi Toyoshima; Fumio Kojima; Akihiro Shimizu (IEEE J. Solid State Circuits, 1992)

A 16-Mb CMOS SRAM with a 2.3- mu m2 single-bit-line memory cell. - Katsuro Sasaki; Kiyotsugu Ueda; Koichi Takasugi; Hiroshi Toyoshima; Koichiro Ishibashi; Toshiaki Yamanaka; Naotaka Hashimoto; Nagatoshi Ohki (IEEE J. Solid State Circuits, 1993)