Incremental-in-time Algorithm for Digital Simulation. - Kiyoung Choi; Sun Young Hwang; Tom Blank (DAC, 1988)

Fast functional simulation: an incremental approach. - Sun Young Hwang; Tom Blank; Kiyoung Choi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

A Self-Timed Divider Using RSD Number System. - Kiyoung Choi; KiJong Lee; Jun-Woo Kang (ICCD, 1994)

An integrated hardware-software cosimulation environment for heterogeneous systems prototyping. - Yongjoo Kim; Kyuseok Kim; Youngsoo Shin; Taekyoon Ahn; Wonyong Sung; Kiyoung Choi; Soonhoi Ha (ASP-DAC, 1995)

Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification. - Yongjoo Kim; Youngsoo Shin; Kyuseok Kim; Jae-Hee Won; Kiyoung Choi (ISCAS, 1995)

Thread-based software synthesis for embedded system design. - Youngsoo Shin; Kiyoung Choi (ED&TC, 1996)

Software synthesis through task decomposition by dependency analysis. - Youngsoo Shin; Kiyoung Choi (ICCAD, 1996)

An integrated hardware-software cosimulation environment with automated interface generation. - Kyuseok Kim; Yongjoo Kim; Youngsoo Shin; Kiyoung Choi (RSP, 1996)

Hardware-Software Codesign of Resource-Constrained Real-Time Systems. - Sungjoo Yoo; Jinhwan Jeon; Seongsoo Hong; Kiyoung Choi (RTCSA, 1996)

Self-timed divider based on RSD number system. - KiJong Lee; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign. - Youngsoo Shin; Kiyoung Choi (CODES, 1997)

Power-conscious High Level Synthesis Using Loop Folding. - Daehong Kim; Kiyoung Choi (DAC, 1997)

Low power high level synthesis by increasing data correlation. - Dongwan Shin; Kiyoung Choi (ISLPED, 1997)

Loop Pipelining in Hardware-Software Partitioning. - Jinhwan Jeon; Kiyoung Choi (ASP-DAC, 1998)

Optimistic distributed timed cosimulation based on thread simulation model. - Sungjoo Yoo; Kiyoung Choi (CODES, 1998)

Rate Assignment for Embedded Reactive Real-Time Systems. - Youngsoo Shin; Kiyoung Choi (EUROMICRO, 1998)

Partial bus-invert coding for power optimization of system level bus. - Youngsoo Shin; Soo-Ik Chae; Kiyoung Choi (ISLPED, 1998)

An Integrated Cosimulation Environment for Heterogeneous Systems Prototyping. - Yongjoo Kim; Kyuseok Kim; Youngsoo Shin; Taekyoon Ahn; Kiyoung Choi (Des. Autom. Embed. Syst., 1998)

Optimizing geographically distributed timed cosimulation by hierarchically grouped messages. - Sungjoo Yoo; Kiyoung Choi (CODES, 1999)

Performance-Driven Scheduling with Bit-Level Chaining. - Sanghun Park; Kiyoung Choi (DAC, 1999)

Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems. - Youngsoo Shin; Kiyoung Choi (DAC, 1999)

Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design. - Byungil Jeong; Sungjoo Yoo; Kiyoung Choi (FPGA, 1999)

Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs. - Byungil Jeong; Sungjoo Yoo; Sunghyun Lee; Kiyoung Choi (ASP-DAC, 2000)

Narrow bus encoding for low power systems. - Youngsoo Shin; Kiyoung Choi (ASP-DAC, 2000)

Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model. - Sungjoo Yoo; Kyoungseok Rha; Youngchul Cho; Jinyong Jung; Kiyoung Choi (CODES, 2000)

Schedulability-driven performance analysis of multiple mode embedded real-time systems. - Youngsoo Shin; Daehong Kim; Kiyoung Choi (DAC, 2000)

Fast Hardware-Software Coverification by Optimistic Execution of Real Processor. - Sungjoo Yoo; Jong-eun Lee; Jinyong Jung; Kyungseok Rha; Youngchul Cho; Kiyoung Choi (DATE, 2000)

Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. - Youngsoo Shin; Kiyoung Choi; Takayasu Sakurai (ICCAD, 2000)

A new cost model for high-level power optimization and its application. - Taekyoon Ahn; Kiyoung Choi; Ki-Hyun Kim; Seong-Kwan Hon (ISCAS, 2000)

Power minimization of functional units partially guarded computation. - Junghwan Choi; Jinhwan Jeon; Kiyoung Choi (ISLPED, 2000)

Low power self-timed Radix-2 division (poster session). - Jae-Hee Won; Kiyoung Choi (ISLPED, 2000)

Optimizing Timed Cosimulation by Hybrid Synchronization. - Sungjoo Yoo; Kiyoung Choi (Des. Autom. Embed. Syst., 2000)

Performance improvement of geographically distributed cosimulation by hierarchically grouped messages. - Sungjoo Yoo; Kiyoung Choi; Dong Sam Ha (IEEE Trans. Very Large Scale Integr. Syst., 2000)

High-level synthesis under multi-cycle interconnect delay. - Jinhwan Jeon; Daehong Kim; Dongwan Shin; Kiyoung Choi (ASP-DAC, 2001)

Scheduling-based code size reduction in processors with indirect addressing mode. - Sungtaek Lim; Jihong Kim 001; Kiyoung Choi (CODES, 2001)

Area-efficient buffer binding based on a novel two-port FIFO structure. - Kyoungseok Rha; Kiyoung Choi (CODES, 2001)

Performance improvement of multi-processor systems cosimulation based on SW analysis. - Jinyong Jung; Sungjoo Yoo; Kiyoung Choi (DATE, 2001)

Behavior-to-Placed RTL Synthesis with Performance-Driven Placement. - Daehong Kim; Jinyong Jung; Sunghyun Lee; Jinhwan Jeon; Kiyoung Choi (ICCAD, 2001)

Low power pipelining of linear systems: a common operand centric approach. - Daehong Kim; Dongwan Shin; Kiyoung Choi (ISLPED, 2001)

Performance-driven high-level synthesis with bit-level chaining andclock selection. - Sanghun Park; Kiyoung Choi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Partial bus-invert coding for power optimization of application-specific systems. - Youngsoo Shin; Soo-Ik Chae; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Narrow bus encoding for low-power DSP systems. - Youngsoo Shin; Kiyoung Choi; Young-Hoon Chang (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Power-conscious Scheduling for Real-time Embedded Systems Design. - Youngsoo Shin; Kiyoung Choi; Takayasu Sakurai (VLSI Design, 2001)

Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model. - Sunghyun Lee; Sungjoo Yoo; Kiyoung Choi (CODES, 2002)

Efficient instruction encoding for automatic instruction set design of configurable ASIPs. - Jong-eun Lee; Kiyoung Choi; Nikil D. Dutt (ICCAD, 2002)

An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model. - Sunghyun Lee; Kiyoung Choi; Sungjoo Yoo (ISLPED, 2002)

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. - Youngchul Cho; Ganghee Lee; Kiyoung Choi; Sungjoo Yoo; Nacer-Eddine Zergainoh (Embedded Software for SoC, 2003)

Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures. - Jong-eun Lee; Kiyoung Choi; Nikil D. Dutt (ASAP, 2003)

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. - Youngchul Cho; Ganghee Lee; Sungjoo Yoo; Kiyoung Choi; Nacer-Eddine Zergainoh (DATE, 2003)

Energy-efficient instruction set synthesis for application-specific processors. - Jong-eun Lee; Kiyoung Choi; Nikil D. Dutt (ISLPED, 2003)

An algorithm for mapping loops onto coarse-grained reconfigurable architectures. - Jong-eun Lee; Kiyoung Choi; Nikil D. Dutt (LCTES, 2003)

Configurable Processors for Embedded Computing. - Nikil D. Dutt; Kiyoung Choi (Computer, 2003)

An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design. - Yongjin Ahn; Daehong Kim; Sunghyun Lee; Sanggyu Park; Sungjoo Yoo; Kiyoung Choi; Soo-Ik Chae (Des. Autom. Embed. Syst., 2003)

Compilation Approach for Coarse-Grained Reconfigurable Architectures. - Jong-eun Lee; Kiyoung Choi; Nikil D. Dutt (IEEE Des. Test Comput., 2003)

Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems. - Mary Kiemb; Kiyoung Choi (CASES, 2004)

A Mobility Analysis Method of Closed-chain Mechanisms with Over-constraints and Non-holonomic Constraints. - Whee Kuk Kim; Kiyoung Choi; Byung-Ju Yi (ICRA, 2004)

Application-specific configuration of multithreaded processor architecture for embedded applications. - Mary Kiemb; Kiyoung Choi (ISCAS (2), 2004)

Scheduler implementation in MP SoC design. - Youngchul Cho; Sungjoo Yoo; Kiyoung Choi; Nacer-Eddine Zergainoh; Ahmed Amine Jerraya (ASP-DAC, 2005)

Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization. - Yoonjin Kim; Mary Kiemb; Chulsoo Park; Jinyong Jung; Kiyoung Choi (DATE, 2005)

Pipelining with common operands for power-efficient linear systems. - Daehong Kim; Dongwan Shin; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Worst case execution time analysis for synthesized hardware. - Jun-hee Yoo; Xingguang Feng; Kiyoung Choi; Eui-Young Chung; Kyu-Myung Choi (ASP-DAC, 2006)

A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. - Minwook Ahn; Jonghee W. Yoon; Yunheung Paek; Yoonjin Kim; Mary Kiemb; Kiyoung Choi (DATE, 2006)

Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. - Yoonjin Kim; Ilhyun Park; Kiyoung Choi; Yunheung Paek (ISLPED, 2006)

Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation. - Imyong Lee; Dongwook Lee; Kiyoung Choi (ASAP, 2007)

Communication Architecture Synthesis of Cascaded Bus Matrix. - Jun-hee Yoo; Dongwook Lee; Sungjoo Yoo; Kiyoung Choi (ASP-DAC, 2007)

Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes. - Youngchul Cho; Nacer-Eddine Zergainoh; Kiyoung Choi; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 2007)

Buffer Size Reduction through Control-Flow Decomposition. - Youngchul Cho; Nacer-Eddine Zergainoh; Ahmed Amine Jerraya; Kiyoung Choi (RTCSA, 2007)

Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration. - Ganghee Lee; Seokhyun Lee; Yongjin Ahn; Kiyoung Choi (ICSAMOS, 2007)

Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture. - Manhwee Jo; V. K. Prasad Arava; Hoonmo Yang; Kiyoung Choi (SoCC, 2007)

Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip. - Youngchul Cho; Nacer-Eddine Zergainoh; Sungjoo Yoo; Ahmed Amine Jerraya; Kiyoung Choi (Des. Autom. Embed. Syst., 2007)

Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction. - Jinyong Jung; Sungjoo Yoo; Kiyoung Choi (Des. Autom. Embed. Syst., 2007)

Instruction set synthesis with efficient instruction encoding for configurable processors. - Jong-eun Lee; Kiyoung Choi; Nikil D. Dutt (ACM Trans. Design Autom. Electr. Syst., 2007)

Entry control in network-on-chip for memory power reduction. - Dongwook Lee; Sungjoo Yoo; Kiyoung Choi (ISLPED, 2008)

A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines. - V. K. Prasad Arava; Manhwee Jo; HyoukJoong Lee; Kiyoung Choi (ISVLSI, 2008)

Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures. - Jong-eun Lee; Kiyoung Choi; Nikil D. Dutt (Int. J. Embed. Syst., 2008)

Introduction to embedded systems week 2006 special issue. - Soonhoi Ha; Kiyoung Choi; Taewhan Kim; Krisztián Flautner; Sang Lyul Min; Wang Yi 001 (ACM Trans. Embed. Comput. Syst., 2008)

SoCDAL: System-on-chip design AcceLerator. - Yongjin Ahn; Keesung Han; Ganghee Lee; Hyunjik Song; Jun-hee Yoo; Kiyoung Choi; Xingguang Feng (ACM Trans. Design Autom. Electr. Syst., 2008)

Code decomposition and recomposition for enhancing embedded software performance. - Youngchul Cho; Kiyoung Choi (ASP-DAC, 2009)

Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency. - Jun-hee Yoo; Sungjoo Yoo; Kiyoung Choi (DAC, 2009)

Coarse-grained reconfigurable architecture for multiple application domains: a case study. - Manhwee Jo; Ganghee Lee; Kyungwook Chang; Kyuseung Han; Kiyoung Choi; Hoonmo Yang; Kiwook Yoon (ICHIT, 2009)

Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture. - Yoonjin Kim; Rabi N. Mahapatra; Ilhyun Park; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus. - Jun-hee Yoo; Sungjoo Yoo; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Thermal-aware fault-tolerant system design with coarse-grained reconfigurable array architecture. - Ganghee Lee; Kiyoung Choi (AHS, 2010)

Memory-Centric Communication Architecture for Reconfigurable Computing. - Kyungwook Chang; Kiyoung Choi (ARC, 2010)

Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture. - Ganghee Lee; Seokhyun Lee; Kiyoung Choi; Nikil D. Dutt (ARC, 2010)

Acceleration of control flow on CGRA using advanced predicated execution. - Kyuseung Han; Jong Kyung Paek; Kiyoung Choi (FPT, 2010)

Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution. - Ganghee Lee; Kyungwook Chang; Kiyoung Choi (IPDPS Workshops, 2010)

Communication architecture design for reconfigurable multimedia SoC platform. - Ganghee Lee; Yongjin Ahn; Seokhyun Lee; Jeongki Son; Kiwook Yoon; Kiyoung Choi (Des. Autom. Embed. Syst., 2010)

Binary acceleration using coarse-grained reconfigurable architecture. - Jong Kyung Paek; Kiyoung Choi; Jong-eun Lee (SIGARCH Comput. Archit. News, 2010)

Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture. - Yoonjin Kim; Rabi N. Mahapatra; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A polynomial-time custom instruction identification algorithm based on dynamic programming. - Junwhan Ahn; Imyong Lee; Kiyoung Choi (ASP-DAC, 2011)

An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors. - Junwhan Ahn; Kiyoung Choi (CODES+ISSS, 2011)

Simulated annealing-based diffusive load balancing on many-core SoC. - Hyunjik Song; Kiyoung Choi (ICAC, 2011)

High-level synthesis with distributed controller for fast timing closure. - Seokhyun Lee; Kiyoung Choi (ICCAD, 2011)

CRM: Configurable Range Memory for Fast Reconfigurable Computing. - Jong Kyung Paek; Jong-eun Lee; Kiyoung Choi (IPDPS Workshops, 2011)

A host-accelerator communication architecture design for efficient binary acceleration. - Yangsu Kim; Kyuseung Han; Kiyoung Choi (ISOCC, 2011)

3D network-on-chip with wireless links through inductive coupling. - Jinho Lee; Mingyang Zhu; Kiyoung Choi; Jung Ho Ahn; Rohit Sharma (ISOCC, 2011)

Resonant properties of piezoelectric cantilever transducers fabricated on the SiC membrane. - Jae Hong Park; Kiyoung Choi; Dong-Yeon Lee; Jaesool Shim; Tae Song Kim (NEMS, 2011)

Coarse-Grained Reconfigurable Array: Architecture and Application Mapping. - Kiyoung Choi (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures. - Ganghee Lee; Kiyoung Choi; Nikil D. Dutt (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Memory-aware mapping and scheduling of tasks and communications on many-core SoC. - Jinho Lee; Kiyoung Choi (ASP-DAC, 2012)

State-based full predication for low power coarse-grained reconfigurable architecture. - Kyuseung Han; Seongsik Park; Kiyoung Choi (DATE, 2012)

Lower-bits cache for low power STT-RAM caches. - Junwhan Ahn; Kiyoung Choi (ISCAS, 2012)

A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problem. - Dongwoo Lee; Junwhan Ahn; Kiyoung Choi (ISOCC, 2012)

Resource-shared custom instruction generation under performance/area constraints. - Di Wu; Junwhan Ahn; Imyong Lee; Kiyoung Choi (ISSoC, 2012)

Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips. - Hanmin Park; Kiyoung Choi (NoCArc@MICRO, 2012)

An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth. - Mingyang Zhu; Jinho Lee; Kiyoung Choi (VLSI-SoC, 2012)

Guest Editorial New Interconnect Technologies in On-Chip Communication. - Kiyoung Choi; John Kim 001; Gabriel H. Loh (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Exploiting New Interconnect Technologies in On-Chip Communication. - John Kim 001; Kiyoung Choi; Gabriel H. Loh (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

ESL Design Methodology. - Deming Chen; Kiyoung Choi; Philippe Coussy; Yuan Xie 001; Zhiru Zhang (J. Electr. Comput. Eng., 2012)

Active Memory Processor for Network-on-Chip-Based Architecture. - Jun-hee Yoo; Sungjoo Yoo; Kiyoung Choi (IEEE Trans. Computers, 2012)

Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (ASP-DAC, 2013)

Deflection routing in 3D Network-on-Chip with TSV serialization. - Jinho Lee; Dongwook Lee; Sunwook Kim; Kiyoung Choi (ASP-DAC, 2013)

Compiling control-intensive loops for CGRAs with state-based full predication. - Kyuseung Han; Kiyoung Choi; Jongeun Lee (DATE, 2013)

Write intensity prediction for energy-efficient non-volatile caches. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (ISLPED, 2013)

Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth. - Gunhee Lee; Jinho Lee; Kiyoung Choi (NoCArc@MICRO, 2013)

Enhancing Utilization of Integer Functional Units for High-Throughput Floating Point Operations on Coarse-Grained Reconfigurable Architecture. - Manhwee Jo; Kyuseung Han; Kiyoung Choi (MUE, 2013)

A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections. - Jinho Lee; Kiyoung Choi (NOCS, 2013)

CPU-based speed acceleration techniques for shear warp volume rendering. - Kiyoung Choi; Sung-Up Jo; Hwamin Lee; Changsung Jeong (Multim. Tools Appl., 2013)

Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA. - Kyuseung Han; Junwhan Ahn; Kiyoung Choi (ACM Trans. Archit. Code Optim., 2013)

Isomorphism-Aware Identification of Custom Instructions With I/O Serialization. - Junwhan Ahn; Kiyoung Choi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint. - Jinho Lee; Moo-Kyoung Chung; Yeon-Gon Cho; Soojung Ryu; Jung Ho Ahn; Kiyoung Choi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Deflection routing in 3D network-on-chip with limited vertical bandwidth. - Jinho Lee; Dongwook Lee; Sunwook Kim; Kiyoung Choi (ACM Trans. Design Autom. Electr. Syst., 2013)

Leveraging parallelism in the presence of control flow on CGRAs. - Jihyun Ryoo; Kyuseung Han; Kiyoung Choi (ASP-DAC, 2014)

Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (DAC, 2014)

DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (HPCA, 2014)

Concept-aware ensemble system for pedestrian detection. - Helin Lin; Kyounghoon Kim; Kiyoung Choi (Intelligent Vehicles Symposium, 2014)

Tree-Mesh Heterogeneous Topology for Low-Latency NoC. - Sungju Han; Jinho Lee; Kiyoung Choi (NoCArc@MICRO, 2014)

An FPGA implementation of high-throughput key-value store using Bloom filter. - Jae Min Cho; Kiyoung Choi (VLSI-DAT, 2014)

Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture. - Dongwoo Lee; Kiyoung Choi (VLSI-SoC (Selected Papers), 2014)

Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study. - Manhwee Jo; Dongwook Lee; Kyuseung Han; Kiyoung Choi (Integr., 2014)

Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture. - Kyuseung Han; Ganghee Lee; Kiyoung Choi (IEEE Trans. Dependable Secur. Comput., 2014)

Critical-path-aware high-level synthesis with distributed controller for fast timing closure. - Seokhyun Lee; Kiyoung Choi (ACM Trans. Design Autom. Electr. Syst., 2014)

Configurable range memory for effective data reuse on programmable accelerators. - Jongeun Lee; Seongseok Seo; Jong Kyung Paek; Kiyoung Choi (ACM Trans. Design Autom. Electr. Syst., 2014)

Introduction to the Special Issue on the 11th International Conference on Field-Programmable Technology (FPT'12). - Jason Helge Anderson; Kiyoung Choi (ACM Trans. Reconfigurable Technol. Syst., 2014)

LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology. - Junwhan Ahn; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2014)

THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures. - Jinho Lee; Junwhan Ahn; Kiyoung Choi; Kyungsu Kang (ASP-DAC, 2015)

A scalable processing-in-memory accelerator for parallel graph processing. - Junwhan Ahn; Sungpack Hong; Sungjoo Yoo; Onur Mutlu; Kiyoung Choi (ISCA, 2015)

PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture. - Junwhan Ahn; Sungjoo Yoo; Onur Mutlu; Kiyoung Choi (ISCA, 2015)

Message from the general chairs. - Naehyuck Chang; Kiyoung Choi (VLSI-SoC, 2015)

Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM. - Namhyung Kim; Junwhan Ahn; Woong Seo; Kiyoung Choi (VLSI-SoC, 2015)

Dynamic error tracking and supply voltage adjustment for low power. - Pierre Nicolas-Nicolaz; Kiyoung Choi (VLSI-SoC, 2015)

REDELF: An Energy-Efficient Deadlock-Free Routing for 3D NoCs with Partial Vertical Connections. - Jinho Lee; Kyungsu Kang; Kiyoung Choi (ACM J. Emerg. Technol. Comput. Syst., 2015)

Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing. - Yiran Chen 001; Kiyoung Choi; Weisheng Zhao (IEEE Trans. Multi Scale Comput. Syst., 2015)

An energy-efficient random number generator for stochastic circuits. - Kyounghoon Kim; Jongeun Lee; Kiyoung Choi (ASP-DAC, 2016)

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks. - Kyounghoon Kim; Jungki Kim; Joonsang Yu; Jungwoo Seo; Jongeun Lee; Kiyoung Choi (DAC, 2016)

Adaptive delay monitoring for wide voltage-range operation. - Jongho Kim; Gunhee Lee; Kiyoung Choi; Yonghwan Kim; Wook Kim; Kyung Tae Do; Jung Yun Choi (DATE, 2016)

Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic. - Jinho Lee; Jung Ho Ahn; Kiyoung Choi (DATE, 2016)

Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array. - Atul Rahman; Jongeun Lee; Kiyoung Choi (DATE, 2016)

A new approach to binarizing neural networks. - Jungwoo Seo; Joonsang Yu; Jongeun Lee; Kiyoung Choi (ISOCC, 2016)

Dynamic clock synchronization scheme between voltage domains in multi-core architecture. - Jaehyun Kim; Kiyoung Choi; Sang-Heon Lee 006; Soojung Ryu (VLSI-SoC, 2016)

Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip. - Hanmin Park; Kiyoung Choi (IET Comput. Digit. Tech., 2016)

Exploration of trade-offs in the design of volatile STT-RAM cache. - Namhyung Kim; Kiyoung Choi (J. Syst. Archit., 2016)

A design framework for hierarchical ensemble of multiple feature extractors and multiple classifiers. - Kyounghoon Kim; Helin Lin; Jin Young Choi; Kiyoung Choi (Pattern Recognit., 2016)

AIM: Energy-Efficient Aggregation Inside the Memory Hierarchy. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (ACM Trans. Archit. Code Optim., 2016)

Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (IEEE Trans. Computers, 2016)

Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching. - Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Scalable stochastic-computing accelerator for convolutional neural networks. - Hyeon Uk Sim; Dong Nguyen 001; Jongeun Lee; Kiyoung Choi (ASP-DAC, 2017)

Incremental training of CNNs for user customization: work-in-progress. - Mansureh S. Moghaddam; Barend Harris; Duseok Kang; Inpyo Bae; Euiseok Kim; Hyemi Min; Hansu Cho; Sukjin Kim; Bernhard Egger 002; Soonhoi Ha; Kiyoung Choi (CASES, 2017)

A space- and energy-efficient code Compression/Decompression technique for coarse-grained reconfigurable architectures. - Bernhard Egger 002; Hochan Lee; Duseok Kang; Mansureh S. Moghaddam; Youngchul Cho; Yeonbok Lee; Sukjin Kim; Soonhoi Ha; Kiyoung Choi (CGO, 2017)

Design space exploration of FPGA accelerators for convolutional neural networks. - Atul Rahman; Sangyun Oh; Jongeun Lee; Kiyoung Choi (DATE, 2017)

FPGA implementation of convolutional neural network based on stochastic computing. - Daewoo Kim; Mansureh S. Moghaddam; Hossein Moradian; Hyeon Uk Sim; Jongeun Lee; Kiyoung Choi (FPT, 2017)

Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks. - Joonsang Yu; Kyounghoon Kim; Jongeun Lee; Kiyoung Choi (ICCD, 2017)

A new stochastic mutiplier for deep neural networks. - Subin Huh; Joonsang Yu; Kiyoung Choi (ISOCC, 2017)

Hybrid spiking-stochastic Deep Neural Network. - Heesu Kim; Joonsang Yu; Kiyoung Choi (VLSI-DAT, 2017)

Synthesis of multi-variate stochastic computing circuits. - Kyounghoon Kim; Kiyoung Choi (VLSI-SoC, 2017)

Optimal mapping of program overlays onto many-core platforms with limited memory capacity. - Mansureh Shahraki Moghaddam; M. Balakrishnan; Kiyoung Choi (Des. Autom. Embed. Syst., 2017)

Autonomic Diffusive Load Balancing on Many-Core Architecture Using Simulated Annealing. - Hyunjik Song; Kiyoung Choi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator. - Jinho Lee; Heesu Kim; Sungjoo Yoo; Kiyoung Choi; H. Peter Hofstee; Gi-Joon Nam; Mark Nutter; Damir A. Jamsek (Proc. VLDB Endow., 2017)

Dirty-Block Tracking in a Direct-Mapped DRAM Cache with Self-Balancing Dispatch. - Dongwoo Lee; Sang-Heon Lee 006; Soojung Ryu; Kiyoung Choi (ACM Trans. Archit. Code Optim., 2017)

Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares. - Jinho Lee; Jongwook Chung; Jung Ho Ahn; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Reconfigurable Architectures. - Mansureh Shahraki Moghaddam; Jae-Min Cho; Kiyoung Choi (Handbook of Hardware/Software Codesign, 2017)

Speaker Verification based on Deep Neural Network for Text-Constrained Short Commands. - Heesu Kim; Euntae Choi; Kiyoung Choi (APSIPA, 2018)

Architectures and algorithms for user customization of CNNs. - Barend Harris; Mansureh S. Moghaddam; Duseok Kang; Inpyo Bae; Euiseok Kim; Hyemi Min; Hansu Cho; Sukjin Kim; Bernhard Egger 002; Soonhoi Ha; Kiyoung Choi (ASP-DAC, 2018)

Training Neural Networks with Low Precision Dynamic Fixed-Point. - Sujeong Jo; Hanmin Park; Gunhee Lee; Kiyoung Choi (ICCD, 2018)

ComPEND: Computation Pruning through Early Negative Detection for ReLU in a Deep Neural Network Accelerator. - Dongwoo Lee; Sungbum Kang; Kiyoung Choi (ICS, 2018)

Tapered-Ratio Compression for Residual Network. - Sungbum Kang; Joonsang Yu; Kiyoung Choi (ISOCC, 2018)

Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks. - Jaehyun Kim; Chaeun Lee; Kiyoung Choi (ISOCC, 2018)

Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators. - Hossein Moradian; Sujeong Jo; Kiyoung Choi (ISOCC, 2018)

Deep neural networks with weighted spikes. - Jaehyun Kim; Heesu Kim; Subin Huh; Jinho Lee; Kiyoung Choi (Neurocomputing, 2018)

Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems. - Namhyung Kim; Junwhan Ahn; Kiyoung Choi; Daniel Sánchez 003; Donghoon Yoo; Soojung Ryu (ACM Trans. Archit. Code Optim., 2018)

An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding. - Aidyn Zhakatayev; Kyounghoon Kim; Kiyoung Choi; Jongeun Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation. - Jongho Kim; Kiyoung Choi; Yonghwan Kim; Wook Kim; Kyung Tae Do; Jung-Hwan Choi (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Network Recasting: A Universal Method for Network Architecture Transformation. - Joonsang Yu; Sungbum Kang; Kiyoung Choi (AAAI, 2019)

Cell division: weight bit-width reduction technique for convolutional neural network hardware accelerators. - Hanmin Park; Kiyoung Choi (ASP-DAC, 2019)

Acceleration of DNN Backward Propagation by Selective Computation of Gradients. - Gunhee Lee; Hanmin Park; Namhyung Kim; Joonsang Yu; Sujeong Jo; Kiyoung Choi (DAC, 2019)

Aging Gracefully with Approximation. - Jongho Kim; Heesu Kim; Hussam Amrouch; Jörg Henkel; Andreas Gerstlauer; Kiyoung Choi (ISCAS, 2019)

VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks. - Jaehyun Kim; Chaeun Lee; Jihun Kim; Yumin Kim; Cheol Seong Hwang; Kiyoung Choi (ISLPED, 2019)

An RRAM-based Analog Neuron Design for the Weighted Spiking Neural network. - Chaeun Lee; Jaehyun Kim; Kiyoung Choi (ISOCC, 2019)

Autoencoder-Based Incremental Class Learning without Retraining on Old Data. - Euntae Choi; Kyungmi Lee; Kiyoung Choi (CoRR, 2019)

Aging Compensation With Dynamic Computation Approximation. - Heesu Kim; Jongho Kim; Hussam Amrouch; Jörg Henkel; Andreas Gerstlauer; Kiyoung Choi; Hanmin Park (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent. - Heesu Kim; Hanmin Park; Taehyun Kim; Kwanheum Cho; Eojin Lee; Soojung Ryu; Hyuk-Jae Lee; Kiyoung Choi; Jinho Lee (HPCA, 2021)

Human-Robot Interaction Force based Power Assistive Algorithm of Upper Limb Exoskeleton Robots Driven by a Series Elastic Actuator. - Deokjin Lee; Kiyoung Choi; Wonbum Yun; Sehoon Oh (IECON, 2022)

ComPreEND: Computation Pruning through Predictive Early Negative Detection for ReLU in a Deep Neural Network Accelerator. - Namhyung Kim; Hanmin Park; Dongwoo Lee; Sungbum Kang; Jinho Lee; Kiyoung Choi (IEEE Trans. Computers, 2022)

ExSLeR: Development of a Robotic Arm for Human Skill Learning. - Deokjin Lee; Kiyoung Choi; Junyoung Kim 003; Wonbum Yun; Taehoon Kim; Kanghyun Nam; Sehoon Oh (AIM, 2023)

Retrospective: A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing. - Junwhan Ahn; Sungpack Hong; Sungjoo Yoo; Onur Mutlu; Kiyoung Choi (CoRR, 2023)

Identification of Flexible Joint Robot Inertia Matrix Using Frequency Response Analysis. - Kiyoung Choi; Junho Song; Wonbum Yun; Deokjin Lee; Sehoon Oh (IROS, 2024)

Low Impedance Rendering Toward Safe Human-Robot Interaction. - Wonbum Yun; Kiyoung Choi; Junyoung Kim 003; Sehoon Oh; Hyun-Joon Chung (HRI, 2025)