Demonstration of ternary devices and circuits using dual channel graphene barristors. - So-Young Kim; Sunwoo Heo; Kiyung Kim; Myungwoo Son; Seung-Mo Kim; Ho-In Lee; Yongsu Lee; Hyeon Jun Hwang; Moon-Ho; Byoung Hun Lee (ISMVL, 2019)

Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction. - Kiyung Kim; Sunmean Kim; Yongsu Lee; Daeyeon Kim; So-Young Kim; Seokhyeong Kang; Byoung Hun Lee (ISMVL, 2020)