Enabling high level design of adaptive systems with partial reconfiguration. - Kizheppatt Vipin; Suhaib A. Fahmy (FPT, 2011)

A threat-based Connect6 implementation on FPGA. - Kizheppatt Vipin; Suhaib A. Fahmy (FPT, 2011)

Efficient region allocation for adaptive partial reconfiguration. - Kizheppatt Vipin; Suhaib A. Fahmy (FPT, 2011)

Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration. - Kizheppatt Vipin; Suhaib A. Fahmy (ARC, 2012)

A high speed open source controller for FPGA Partial Reconfiguration. - Kizheppatt Vipin; Suhaib A. Fahmy (FPT, 2012)

An approach for redundancy in FlexRay networks using FPGA partial reconfiguration. - Shanker Shreejith; Kizheppatt Vipin; Suhaib A. Fahmy; Martin Lukasiewycz (DATE, 2013)

An Approach to a Fully Automated Partial Reconfiguration Design Flow. - Kizheppatt Vipin; Suhaib A. Fahmy (FCCM, 2013)

System-level FPGA device driver with high-level synthesis support. - Kizheppatt Vipin; Shanker Shreejith; Dulitha Gunasekera; Suhaib A. Fahmy; Nachiket Kapre (FPT, 2013)

Automated Partitioning for Partial Reconfiguration Design of Adaptive Systems. - Kizheppatt Vipin; Suhaib A. Fahmy (IPDPS Workshops, 2013)

Mapping Time-Critical Safety-Critical Cyber Physical Systems to Hybrid FPGAs. - Kizheppatt Vipin; Shanker Shreejith; Suhaib A. Fahmy; Arvind Easwaran (CPSNA, 2014)

Automated Partial Reconfiguration Design for Adaptive Systems with CoPR for Zynq. - Kizheppatt Vipin; Suhaib A. Fahmy (FCCM, 2014)

DyRACT: A partial reconfiguration enabled accelerator and test platform. - Kizheppatt Vipin; Suhaib A. Fahmy (FPL, 2014)

ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq. - Kizheppatt Vipin; Suhaib A. Fahmy (IEEE Embed. Syst. Lett., 2014)

Mapping adaptive hardware systems with partial reconfiguration using CoPR for Zynq. - Kizheppatt Vipin; Suhaib A. Fahmy (AHS, 2015)

Virtualized FPGA Accelerators for Efficient Cloud Computing. - Suhaib A. Fahmy; Kizheppatt Vipin; Shanker Shreejith (CloudCom, 2015)

Dynamic Cognitive Radios on the Xilinx Zynq Hybrid FPGA. - Shanker Shreejith; Bhaskar Banarjee; Kizheppatt Vipin; Suhaib A. Fahmy (CrownCom, 2015)

MiCAP: a custom reconfiguration controller for dynamic circuit specialization. - Amit Kulkarni 002; Kizheppatt Vipin; Dirk Stroobandt (ReConFig, 2015)

Design automation for partially reconfigurable adaptive systems - Vipin Kizheppatt (2015)

Designing a virtual runtime for FPGA accelerators in the cloud. - Mikhail Asiatici; Nithin George; Kizheppatt Vipin; Suhaib A. Fahmy; Paolo Ienne (FPL, 2016)

JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication. - Malte Vesper; Dirk Koch; Kizheppatt Vipin; Suhaib A. Fahmy (FPL, 2016)

Enabling partial reconfiguration and low latency routing using segmented FPGA NoCs. - Kizheppatt Vipin; Jan Gray; Nachiket Kapre (FPL, 2017)

Virtualized Execution Runtime for FPGA Accelerators in the Cloud. - Mikhail Asiatici; Nithin George; Kizheppatt Vipin; Suhaib A. Fahmy; Paolo Ienne (IEEE Access, 2017)

CANNoC: An open-source NoC architecture for ECU consolidation. - Kizheppatt Vipin (MWSCAS, 2018)

Memristor-based Synaptic Sampling Machines. - Irina Dolzhikova; Khaled N. Salama; Vipin Kizheppatt; Alex Pappachen James (CoRR, 2018)

FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications. - Kizheppatt Vipin; Suhaib A. Fahmy (ACM Comput. Surv., 2018)

ZyNet: Automating Deep Neural Network Implementation on Low-Cost Reconfigurable Edge Computing Platforms. - Kizheppatt Vipin (FPT, 2019)

HBLast: An Open-Source FPGA Library for DNA Sequencing Acceleration. - Marzhan Bekbolat; Sabina Kairatova; Ayan Shymyrbay; Kizheppatt Vipin (IPDPS Workshops, 2019)

Reconfigurable Threshold Logic Networks in FPGA for Moving Object Detection. - Alex Pappachen James; Bhaskar Choubey; Kizheppatt Vipin (MWSCAS, 2019)

OpenNoC: An Open-Source NoC Infrastructure for FPGA-Based Hardware Acceleration. - Kuladeep Sai Reddy; Kizheppatt Vipin (IEEE Embed. Syst. Lett., 2019)

AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation. - Kizheppatt Vipin (Int. J. Reconfigurable Comput., 2019)

StocNoC: Accelerating Stochastic Models Through Reconfigurable Network on Chip Architectures. - Arshyn Zhanbolatov; Kizheppatt Vipin; Aresh Dadlani; Dmitriy Fedorov (ARC, 2020)

High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay. - Xiangwei Li; Kizheppatt Vipin; Douglas L. Maskell; Suhaib A. Fahmy; Abhishek Kumar Jain (ISCAS, 2020)

On the Suitability of Read only Memory for FPGA-Based CAM Emulation Using Partial Reconfiguration. - Muhammad Irfan 004; Kizheppatt Vipin; Ray C. C. Cheung (ARC, 2021)

Reconfigurable Wireless PHY with Dynamically Controlled Out-of-Band Emission on Zynq SoC. - Aakanksha Tewari; Neelam Singh; Sumit Jagdish Darak; Vipin Kizheppatt; Mohammed Sajjad Jafri (MWSCAS, 2022)

Accelerating DNA Sequence Analysis using Content-Addressable Memory in FPGAs. - Muhammad Irfan 004; Kizheppatt Vipin; Rizwan Qureshi (SmartCloud, 2023)

FCSec: An Open-source Testbed for Security Evaluation on UAV Communications. - Indu Chandran; Mukesh Narayana Gadde; Kizheppatt Vipin (TrustCom, 2024)

A PUF secured lightweight mutual authentication protocol for multi-UAV networks. - Indu Chandran; Kizheppatt Vipin (Comput. Networks, 2024)

Decentralized multi-hop data processing in UAV networks using MARL. - Indu Chandran; Kizheppatt Vipin (Veh. Commun., 2024)

Multi-UAV Networks for Disaster Monitoring: Challenges and Opportunities from a Network Perspective. - Indu Chandran; Kizheppatt Vipin (SN Comput. Sci., 2024)

Heterogeneous Multi-UAV Ad-Hoc Networks for Surveillance and Wireless Coverage in Challenging Terrain to Enhance Disaster Missions. - Indu Chandran; R. Gopika; K. P. Anagha Rajendran; Vipin Kizheppatt (SN Comput. Sci., 2024)

A cross-layer PUF-secured energy and congestion-aware on-demand routing for multi-UAV networks. - Indu Chandran; Kizheppatt Vipin (Comput. Networks, 2025)