Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms. - Klaas L. Hofstra; Sabih H. Gerez (HiPEAC, 2007)

RF Performance of T-DAB Receivers. - Roel Schiphorst; Jordy Potman; Klaas L. Hofstra; Harm S. Cronie; Cornelis H. Slump (IEEE Trans. Broadcast., 2008)

26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology. - Anant Singh; Dario Albino Carnelli; Altay Falay; Klaas L. Hofstra; Fabio Licciardello; Kia Salimi; Hugo Santos; Amin Shokrollahi; Roger Ulrich; Christoph Walter; John Fox; Peter Hunt; et al. (ISSCC, 2014)

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS. - Amin Shokrollahi; Dario Albino Carnelli; John Fox; Klaas L. Hofstra; Brian Holden; Ali Hormati; Peter Hunt; Margaret Johnston; John Keay; Sergio Pesenti; Richard Simpson 004; David Stauffer; et al. (ISSCC, 2016)

A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET. - Armin Tajalli; Mani Bastani Parizi; Dario Albino Carnelli; Chen Cao; John Fox; Kiarash Gharibdoust; Davide Gorret; Amit Gupta; Christopher Hall; Ahmed Hassanin; Klaas L. Hofstra; Brian Holden; et al. (VLSI Circuits, 2019)

Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ. - Armin Tajalli; Mani Bastani Parizi; Dario Albino Carnelli; Chen Cao; Kiarash Gharibdoust; Amit Gupta; Ahmed Hassanin; Klaas L. Hofstra; Brian Holden; Ali Hormati; John Keay; Amin Shokrollahi; et al. (CICC, 2020)

A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET. - Armin Tajalli; Mani Bastani Parizi; Dario Albino Carnelli; Chen Cao; Kiarash Gharibdoust; Davide Gorret; Amit Gupta; Christopher Hall; Ahmed Hassanin; Klaas L. Hofstra; Brian Holden; Ali Hormati; et al. (IEEE J. Solid State Circuits, 2020)