Dynamic delay variation behaviour of RNS multiply-add architectures. - Kleanthis Papachatzopoulos; Ioannis Kouretas; Vassilis Paliouras (ISCAS, 2016)

Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability. - Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders. - Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations. - Kleanthis Papachatzopoulos; Vassilis Paliouras (ARITH, 2020)

Novel Noise-Shaping Stochastic-Computing Converters for Digital Filtering. - Kleanthis Papachatzopoulos; Chris Andriakopoulos; Vassilis Paliouras (ISCAS, 2020)

A Novel Stochastic Polar Architecture for All-Digital Transmission. - Chris Andriakopoulos; Kleanthis Papachatzopoulos; Vassilis Paliouras (ISCAS, 2021)

Sum Propagate Adders. - Giorgos Dimitrakopoulos; Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Emerg. Top. Comput., 2021)

Sensitivity to Threshold Voltage Variations of Exact and Incomplete Prefix Addition Trees. - Kleanthis Papachatzopoulos; Vassilis Paliouras (ISCAS, 2022)

Path-Based Delay Variation Models for Parallel-Prefix Adders. - Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Emerg. Top. Comput., 2023)

Noise-Shaping Binary-to-Stochastic Converters for Reduced-Length Bit-Streams. - Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Emerg. Top. Comput., 2023)